Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 141 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
5 DDS 0 R/W DMAC Single Address Transfer Option
Selects whether full access is always performed
or burst access is enabled when DMAC single
address transfer is performed on the
DRAM/synchronous DRAM interface.
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst
access, DMAC single address transfer is
performed in full access mode regardless of the
setting of this bit.
This bit has no effect on other bus master
external accesses or DMAC dual address
transfers.
0: Full access is always executed
1: Burst access is enabled
4 EDDS 0 R/W EXDMAC Single Address Transfer Option
Selects whether full access is always performed
or burst access is enabled when EXDMAC
single address transfer is performed on the
DRAM/synchronous DRAM interface.
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst
access, EXDMAC single address transfer is
performed in full access mode regardless of the
setting of this bit.
This bit has no effect on other bus master
external accesses or EXDMAC dual address
transfers.
0: Full access is always executed
1: Burst access is enabled
3 — 0R/WReserved
This bit can be read from or written to.
However, the write value should always be 0.