Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 140 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
7 BE 0 R/W Burst Access Enable
Selects enabling or disabling of burst access to
areas designated as DRAM/continuous
synchronous DRAM space. DRAM/continuous
synchronous DRAM space burst access is
performed in fast page mode. When using EDO
page mode DRAM, the OE signal must be
connected.
0: Full access
1: Access in fast page mode
6 RCDM 0 R/W RAS Down Mode
When access to DRAM space is interrupted by
an access to normal bus space, an access to
an internal I/O register, etc., this bit selects
whether the RAS signal is held low while
waiting for the next DRAM access (RAS down
mode), or is driven high again (RAS up mode).
The setting of this bit is valid only when the BE
bit is set to 1.
If this bit is cleared to 0 when set to 1 in the
R
AS down state, the
R
AS down state is cleared
at that point, and RAS goes high.
When continuous synchronous DRAM space is
set, reading from and writing to this bit is
enabled. However, the setting does not affect
the operation.
0: RAS up mode selected for DRAM space
access
1: RAS down mode selected for DRAM space
access