Datasheet

Rev. 3.00 Mar 17, 2006 page xvii of l
6.7.9 Precharge State Count.......................................................................................... 208
6.7.10 Bus Cycle Control in Write Cycle ....................................................................... 210
6.7.11 Byte Access Control ............................................................................................ 211
6.7.12 Burst Operation.................................................................................................... 214
6.7.13 Refresh Control.................................................................................................... 217
6.7.14 Mode Register Setting of Synchronous DRAM................................................... 223
6.7.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous
DRAM Interface .................................................................................................. 224
6.8 Burst ROM Interface......................................................................................................... 229
6.8.1 Basic Timing........................................................................................................ 229
6.8.2 Wait Control ........................................................................................................ 231
6.8.3 Write Access........................................................................................................ 231
6.9 Idle Cycle.......................................................................................................................... 232
6.9.1 Operation ............................................................................................................. 232
6.9.2 Pin States in Idle Cycle........................................................................................ 249
6.10 Write Data Buffer Function .............................................................................................. 249
6.11 Bus Release....................................................................................................................... 250
6.11.1 Operation ............................................................................................................. 251
6.11.2 Pin States in External Bus Released State............................................................ 252
6.11.3 Transition Timing ................................................................................................ 253
6.12 Bus Arbitration.................................................................................................................. 255
6.12.1 Operation ............................................................................................................. 255
6.12.2 Bus Transfer Timing............................................................................................ 255
6.13 Bus Controller Operation in Reset.................................................................................... 257
6.14 Usage Notes ...................................................................................................................... 257
6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 257
6.14.2 External Bus Release Function and Software Standby........................................ 257
6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing............... 258
6.14.4 BREQO Output Timing ....................................................................................... 258
6.14.5 Notes on Usage of the Synchronous DRAM ....................................................... 258
Section 7 DMA Controller (DMAC)............................................................................. 259
7.1 Features............................................................................................................................. 259
7.2 Input/Output Pins.............................................................................................................. 261
7.3 Register Descriptions........................................................................................................ 261
7.3.1 Memory Address Registers (MARA and MARB)............................................... 263
7.3.2 I/O Address Registers (IOARA and IOARB)...................................................... 263
7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) .................................. 264
7.3.4 DMA Control Registers (DMACRA and DMACRB) ......................................... 265
7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)............. 272
7.3.6 DMA Write Enable Register (DMAWER).......................................................... 283