Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 134 of 926
REJ09B0283-0300
T
h
Address
T
1
T
2
T
3
T
t
Bus cycle
Data
HWR, LWR
Write
Data
RD
CS
Read
Figure 6.3 CS
CSCS
CS and Address Assertion Period Extension (Example of 3-State Access Space
and RDNn = 0)
