Datasheet

Rev. 3.00 Mar 17, 2006 page xvi of l
6.3.7 Bus Control Register (BCR) ................................................................................ 136
6.3.8 DRAM Control Register (DRAMCR) ................................................................. 138
6.3.9 DRAM Access Control Register (DRACCR)...................................................... 144
6.3.10 Refresh Control Register (REFCR) ..................................................................... 149
6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 152
6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... 152
6.4 Bus Control....................................................................................................................... 152
6.4.1 Area Division....................................................................................................... 152
6.4.2 Bus Specifications................................................................................................ 154
6.4.3 Memory Interfaces............................................................................................... 156
6.4.4 Chip Select Signals .............................................................................................. 157
6.5 Basic Bus Interface ........................................................................................................... 158
6.5.1 Data Size and Data Alignment............................................................................. 158
6.5.2 Valid Strobes........................................................................................................ 160
6.5.3 Basic Operation Timing....................................................................................... 160
6.5.4 Wait Control ........................................................................................................ 169
6.5.5 Read Strobe (RD) Timing.................................................................................... 170
6.5.6 Extension of Chip Select (CS) Assertion Period.................................................. 171
6.6 DRAM Interface ............................................................................................................... 173
6.6.1 Setting DRAM Space........................................................................................... 173
6.6.2 Address Multiplexing........................................................................................... 173
6.6.3 Data Bus............................................................................................................... 174
6.6.4 Pins Used for DRAM Interface............................................................................ 175
6.6.5 Basic Timing........................................................................................................ 176
6.6.6 Column Address Output Cycle Control............................................................... 177
6.6.7 Row Address Output State Control...................................................................... 178
6.6.8 Precharge State Control ....................................................................................... 180
6.6.9 Wait Control ........................................................................................................ 181
6.6.10 Byte Access Control ............................................................................................ 184
6.6.11 Burst Operation.................................................................................................... 185
6.6.12 Refresh Control.................................................................................................... 190
6.6.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface.... 195
6.7 Synchronous DRAM Interface.......................................................................................... 198
6.7.1 Setting Continuous Synchronous DRAM Space.................................................. 198
6.7.2 Address Multiplexing........................................................................................... 199
6.7.3 Data Bus............................................................................................................... 200
6.7.4 Pins Used for Synchronous DRAM Interface...................................................... 200
6.7.5 Synchronous DRAM Clock ................................................................................. 202
6.7.6 Basic Operation Timing....................................................................................... 202
6.7.7 CAS Latency Control........................................................................................... 204
6.7.8 Row Address Output State Control...................................................................... 206