Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 125 of 926
REJ09B0283-0300
Name Symbol I/O Function
Data transfer acknowledge
1 (EXDMAC)
EDACK1 Output Data transfer acknowledge signal for single
address transfer by EXDMAC channel 1.
Data transfer acknowledge
0 (EXDMAC)
EDACK0 Output Data transfer acknowledge signal for single
address transfer by EXDMAC channel 0.
Note: * These pins are not supported in the H8S/2678 Group.
6.3 Register Descriptions
The bus controller has the following registers.
• Bus width control register (ABWCR)
• Access state control register (ASTCR)
• Wait control register AH (WTCRAH)
• Wait control register AL (WTCRAL)
• Wait control register BH (WTCRBH)
• Wait control register BL (WTCRBL)
• Read strobe timing control register (RDNCR)
• CS assertion period control register H (CSACRH)
• CS assertion period control register L (CSACRL)
• Area 0 burst ROM interface control register (BROMCRH)
• Area 1 burst ROM interface control register (BROMCRL)
• Bus control register (BCR)
• DRAM control register (DRAMCR)
• DRAM access control register (DRACCR)
• Refresh control register (REFCR)
• Refresh timer counter (RTCNT)
• Refresh time constant register (RTCOR)