Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 123 of 926
REJ09B0283-0300
6.2 Input/Output Pins
Table 6.1 shows the pin configuration of the bus controller.
Table 6.1 Pin Configuration
Name Symbol I/O Function
Address strobe AS Output Strobe signal indicating that basic bus interface
space is accessed and address output on
address bus is enabled.
Read RD Output Strobe signal indicating that basic bus interface
space is being read.
High write/write enable HWR Output Strobe signal indicating that basic bus interface
space is written to, and upper half (D15 to D8)
of data bus is enabled or DRAM interface
space write enable signal.
Low write LWR Output Strobe signal indicating that basic bus interface
space is written to, and lower half (D7 to D0) of
data bus is enabled.
Chip select 0 CS0 Output Strobe signal indicating that area 0 is selected.
Chip select 1 CS1 Output Strobe signal indicating that area 1 is selected
Chip select 2/row address
strobe 2/row address
strobe
*
CS2/
RAS2/
*
RAS
*
Output Strobe signal indicating that area 2 is selected,
DRAM row address strobe signal when area 2
is DRAM interface space or areas 2 to 5 are set
as continuous DRAM interface space, or row
address strobe signal of the synchronous
DRAM when the synchronous DRAM interface
is selected.
Chip select 3/row address
strobe 3/column address
strobe
*
CS3/
RAS3/
*
CAS
*
Output Strobe signal indicating that area 3 is selected,
DRAM row address strobe signal when area 3
is DRAM interface space, or column address
strobe signal of the synchronous DRAM when
the synchronous DRAM interface is selected.
Chip select 4/row address
strobe 4/write enable
*
CS4/
RAS4/
*
WE
*
Output Strobe signal indicating that area 4 is selected,
DRAM row address strobe signal when area 4
is DRAM interface space, or write enable signal
of the synchronous DRAM when the
synchronous DRAM interface is selected.