Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Mar 17, 2006 page 118 of 926
REJ09B0283-0300
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt
source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in the TPU’s
TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
Internal
address bus
Internal
write signal
φ
TCIEV
TCFV
TCIV
interrupt signal
TIER_0 write cycle by CPU
TCIV exception handling
TIER_0 address
Figure 5.7 Contention between Interrupt Generation and Disabling
5.7.2 Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3 Times when Interrupts are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.