Datasheet

Rev. 3.00 Mar 17, 2006 page xv of l
Section 5 Interrupt Controller .......................................................................................... 85
5.1 Features............................................................................................................................. 85
5.2 Input/Output Pins.............................................................................................................. 87
5.3 Register Descriptions........................................................................................................87
5.3.1 Interrupt Control Register (INTCR)..................................................................... 88
5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................ 88
5.3.3 IRQ Enable Register (IER) .................................................................................. 91
5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 92
5.3.5 IRQ Status Register (ISR).................................................................................... 98
5.3.6 IRQ Pin Select Register (ITSR)........................................................................... 98
5.3.7 Software Standby Release IRQ Enable Register (SSIER)................................... 100
5.4 Interrupt Sources............................................................................................................... 101
5.4.1 External Interrupts ............................................................................................... 101
5.4.2 Internal Interrupts................................................................................................. 102
5.5 Interrupt Exception Handling Vector Table...................................................................... 102
5.6 Interrupt Control Modes and Interrupt Operation............................................................. 107
5.6.1 Interrupt Control Mode 0..................................................................................... 108
5.6.2 Interrupt Control Mode 2..................................................................................... 110
5.6.3 Interrupt Exception Handling Sequence .............................................................. 112
5.6.4 Interrupt Response Times .................................................................................... 114
5.6.5 DTC and DMAC Activation by Interrupt............................................................ 115
5.7 Usage Notes ...................................................................................................................... 117
5.7.1 Contention between Interrupt Generation and Disabling..................................... 117
5.7.2 Instructions that Disable Interrupts...................................................................... 118
5.7.3 Times when Interrupts are Disabled .................................................................... 118
5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 119
5.7.5 Change of IRQ Pin Select Register (ITSR) Setting ............................................. 119
5.7.6 Note on IRQ Status Register (ISR)...................................................................... 119
Section 6 Bus Controller (BSC)...................................................................................... 121
6.1 Features............................................................................................................................. 121
6.2 Input/Output Pins.............................................................................................................. 123
6.3 Register Descriptions........................................................................................................ 125
6.3.1 Bus Width Control Register (ABWCR)............................................................... 126
6.3.2 Access State Control Register (ASTCR) ............................................................. 126
6.3.3 Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)........................................... 127
6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................ 132
6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)................... 133
6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL).............................. 135