Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Mar 17, 2006 page 117 of 926
REJ09B0283-0300
(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or
CPU interrupt factor, these operate independently.
Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification
of the DTA bit of DMAC’s DMABCR, the DTCE bit of DTC’s DTCERA to DTCERH, and the
DISEL bit of DTC’s MRB.
Table 5.6 Interrupt Source Selection and Clearing Control
Settings
DMAC DTC Interrupt Sources Selection/Clearing Control
DTA DTCE DISEL DMAC DTC CPU
00*
X
10
X
1
1 **
XX
Legend:
: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
: The relevant interrupt is used. The interrupt source is not cleared.
X : The relevant interrupt cannot be used.
* :Don’t care
Note: The SCI or A/D converter interrupt source is cleared when the DMAC or DTC reads or
writes to the prescribed register, and is not dependent upon the DTA bit or DISEL bit.
5.7 Usage Notes
5.7.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher