Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Mar 17, 2006 page 116 of 926
REJ09B0283-0300
DMAC
Selection
circuit
DTCER
DTVECR
Control logic
Determination of
priority
CPU
DTC
Select
signal
IRQ
interrupt
On-chip
supporting
module
Disable signal
Clear signal
Clear signal
Interrupt controller
I, I2 to I0
Interrupt source
clear signal
Interrupt
request
DTC activation
request vector
number
CPU interrupt
request vector
number
SWDTE
clear signal
Clear signal
Figure 5.6 DTC, DMAC, and Interrupt Controller
(1) Selection of Interrupt Source: The activation factors for each channel of DMAC are selected
by DTF3 to DTF0 bits of DMACR. The DTA bit of DMABCR can be used to select whether the
selected activation factors are managed by DMAC. By setting the DTA bit to 1, the interrupt
factor which were the activation factor for that DMAC do not act as the DTC activation factor or
the CPU interrupt factor.
Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation
source or CPU interrupt source by the DTCE bit of DTCERA to DTCERF of DTC.
By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after
DTC data transfer, and request a CPU interrupt.
If DTC carries out the designate number of data transfers and the transfer counter reads 0, after
DTC data transfer, the DTCE bit is also cleared to 0, and an interrupt is requested to the CPU.
(2) Determination of Priority: The DTC activation source is selected in accordance with the
default priority order, and is not affected by mask or priority levels. See table 9.1 for the respective
priority. DMAC inputs activation factor directly to each channel.