Datasheet

Rev. 3.00 Mar 17, 2006 page xiv of l
2.7.8 Memory Indirect—@@aa:8 ................................................................................ 51
2.7.9 Effective Address Calculation ............................................................................. 53
2.8 Processing States............................................................................................................... 55
2.9 Usage Note........................................................................................................................ 56
2.9.1 Usage Notes on Bit-wise Operation Instructions................................................. 56
Section 3 MCU Operating Modes .................................................................................. 57
3.1 Operating Mode Selection ................................................................................................ 57
3.2 Register Descriptions........................................................................................................58
3.2.1 Mode Control Register (MDCR) ......................................................................... 59
3.2.2 System Control Register (SYSCR)...................................................................... 59
3.3 Operating Mode Descriptions........................................................................................... 61
3.3.1 Mode 1................................................................................................................. 61
3.3.2 Mode 2................................................................................................................. 61
3.3.3 Mode 3................................................................................................................. 61
3.3.4 Mode 4................................................................................................................. 61
3.3.5 Mode 5................................................................................................................. 62
3.3.6 Mode 6................................................................................................................. 62
3.3.7 Mode 7................................................................................................................. 62
3.3.8 Mode 10............................................................................................................... 63
3.3.9 Mode 11............................................................................................................... 63
3.3.10 Mode 12............................................................................................................... 63
3.3.11 Mode 13............................................................................................................... 63
3.3.12 Mode 14............................................................................................................... 63
3.3.13 Mode 15............................................................................................................... 63
3.3.14 Pin Functions ....................................................................................................... 63
3.4 Memory Map in Each Operating Mode ............................................................................ 65
Section 4 Exception Handling ......................................................................................... 75
4.1 Exception Handling Types and Priority............................................................................ 75
4.2 Exception Sources and Exception Vector Table............................................................... 75
4.3 Reset.................................................................................................................................. 77
4.3.1 Reset exception handling ..................................................................................... 77
4.3.2 Interrupts after Reset............................................................................................ 79
4.3.3 On-Chip Peripheral Functions after Reset Release.............................................. 79
4.4 Traces................................................................................................................................ 80
4.5 Interrupts........................................................................................................................... 80
4.6 Trap Instruction................................................................................................................. 81
4.7 Stack Status after Exception Handling.............................................................................. 82
4.8 Usage Note........................................................................................................................ 83