Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Mar 17, 2006 page 102 of 926
REJ09B0283-0300
IRQn interrupt
request
IRQnE
IRQnF
S
R
Q
Clear signal
Edge/
level detection
circuit
IRQnSCA, IRQnSCB
IRQn
input
Note: n = 15 to 0
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0
5.4.2 Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.
• The interrupt priority level can be set by means of IPR.
• The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request.
• When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt
control mode or CPU interrupt mask bit.
5.5 Interrupt Exception Handling Vector Table
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. When interrupt control
mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.