Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Mar 17, 2006 page 101 of 926
REJ09B0283-0300
5.4 Interrupt Sources
5.4.1 External Interrupts
There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to
restore the chip from software standby mode.
NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is
always accepted by the CPU regardless of the interrupt control mode or the status of the CPU
interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is
requested at a rising edge or a falling edge on the NMI pin.
IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins
IRQ15 to IRQ0. Interrupts IRQ15 to IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ15 to IRQ0.
• Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to
0 by software.
When IRQ15 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ should
be held low until an interrupt handling starts. Then the corresponding IRQ should be set to high in
the interrupt handling routine and clear the IRQnF bit (n = 0 to 15) in ISR to 0. Interrupts may not
be executed when the corresponding IRQ is set to high before the interrupt handling starts.
Detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been set
for input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2.