Datasheet

Section 4 Exception Handling
Rev. 3.00 Mar 17, 2006 page 82 of 926
REJ09B0283-0300
4.7 Stack Status after Exception Handling
Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
CCR
CCR
*
1
PC (16 bits)
SP
EXR
Reserved
*
1
CCR
CCR
*
1
PC (16 bits)
SP
CCR
PC (24 bits)
SP
EXR
Reserved
*
1
CCR
PC (24 bits)
SP
(a) Normal Modes
*
2
(b) Advanced Modes
Interrupt control mode 0 Interrupt control mode 2
Interrupt control mode 0 Interrupt control mode 2
Notes: 1.
2.
Ignored on return.
Normal modes are not available in this LSI.
Figure 4.3 Stack Status after Exception Handling