Datasheet

Section 4 Exception Handling

Rev. 3.00 Mar 17, 2006 page 79 of 926

REJ09B0283-0300

RES

HWR, LWR

D15 to D0

High

* * *

Address bus

Vector fetch

Internal

processing

Prefetch of first

program instruction

(1)

(2) (4) (6)

(3) (5)

(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)

(2)(4) Start address (contents of reset exception handling vector address)

(5) Start address ((5)=(2)(4))

(6) First program instruction

Note: * Seven program wait states are inserted.

Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled)

4.3.2 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and

CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,

including NMI, are disabled immediately after a reset. Since the first instruction of a program is

always executed immediately after the reset state ends, make sure that this instruction initializes

the stack pointer (example: MOV.L #xx: 32, SP).

4.3.3 On-Chip Peripheral Functions after Reset Release

After reset release, MSTPCR is initialized to H'0FFF and all modules except the DMAC,

EXDMAC and the DTC enter module stop mode.