Datasheet

Section 4 Exception Handling
Rev. 3.00 Mar 17, 2006 page 77 of 926
REJ09B0283-0300
Vector Address
*
1
Exception Source Vector Number Normal Mode
*
2
Advanced Mode
External interrupt IRQ13 29 H'003A to H'003B H'0074 to H'0077
IRQ14 30 H'003C to H'003D H'0078 to H'007B
IRQ15 31 H'003E to H'003F H'007C to H'007F
Internal interrupt
*
3
32

99
H'0040 to H'0041

H'00C6 to H'00C7
H'0080 to H'0083

H'018C to H'018F
Notes: 1. Lower 16 bits of the address.
2. Not available in this LSI.
3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.
4.3 Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 14,
Watchdog Timer.
The interrupt control mode is 0 immediately after reset.
4.3.1 Reset exception handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.1 and 4.2 show examples of the reset sequence.