Datasheet

Section 3 MCU Operating Modes
Rev. 3.00 Mar 17, 2006 page 59 of 926
REJ09B0283-0300
3.2.1 Mode Control Register (MDCR)
MDCR monitors the current operating mode of the H8S/2678 Group chip.
Bit Bit Name Initial Value R/W Descriptions
7 to
3
— All 0 — Reserved
These bits are always read as 0 and cannot be
modified.
2
1
0
MDS2
MDS1
MDS0
—*
—*
—*
R
R
R
Mode Select 2 to 0
These bits indicate the input levels at pins MD2 to
MD0 (the current operating mode). Bits MDS2 to
MDS0 correspond to MD2 to MD0. MDS2 to MDS0
are read-only bits and they cannot be written to. The
mode pin (MD2 to MD0) input levels are latched into
these bits when MDCR is read. These latches are
canceled by a reset.
Note: * Determined by pins MD2 to MD0.
3.2.2 System Control Register (SYSCR)
SYSCR selects saturating or non-saturating calculation for the MAC instruction, controls CPU
access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), sets
external bus mode, and enables or disables on-chip RAM.
Bit Bit Name Initial Value R/W Descriptions
7, 6 — All 1 R/W Reserved
The initial value should not be modified.
5 MACS 0 R/W MAC Saturation
Selects either saturating or non-saturating calculation
for the MAC instruction.
0: Non-saturating calculation for MAC instruction
1: Saturating calculation for MAC instruction
4— 0 R/WReserved
The initial value should not be modified.