Datasheet

Section 2 CPU
Rev. 3.00 Mar 17, 2006 page 56 of 926
REJ09B0283-0300
Exception
handling state
Bus-released state
Software standby
mode
Reset state
*
1
Sleep mode
Power down state
*
3
Program execution state
End of bus request
Bus request
RES = High
STBY = High,
RES = Low
Reset state
Hardware standby
mode
*
2
End of bus request
Bus request
Request for exception handling
Interrupt reque
st
External interrupt request
SSBY = 0
SLEEP
instruction
SSBY = 1
SLEEP instruction
End of exception handling
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low.
A transition can also be made to the reset state when the watchdog timer overflows.
2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.
3. For details, refer to section 22, Power-Down Modes.
Figure 2.13 State Transitions
2.9 Usage Note
2.9.1 Usage Notes on Bit-wise Operation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate
the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore,
special care is necessary to use these instructions for the registers and the ports that include write-
only bit.
The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time,
if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the
flag beforehand.