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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 16-Bit 33 MHz I/O number 103

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas

Electronics Corporation took over all the business of both

companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (981 pages)

PAGE 1
To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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User’s Manual 16 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2678 Group, H8S/2678R Group, H8S/2676 F-ZTATTM Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series H8S/2676 HD64F2676 HD6432676 H8S/2675 HD6432675 H8S/2674R HD6412674R H8S/2673 HD6432673 H8S/2670 HD6412670 Rev.3.00 2006.
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions in This Edition 5. Contents 6. Overview 7. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
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Preface The H8S/2678 Group and H8S/2678R Group are microcomputers (MCU) made up of the H8S/2600 CPU employing Renesas’ original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a 16-Mbyte linear address space.
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In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 23, List of Registers.
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Main Revisions in This Edition Item Page Revision (See Manual for Details) All — All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from “series” to “group” 6.2 Input/Output Pins 124 Symbols amended Table 6.
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Item Page Revision (See Manual for Details) 10.2.4 Pin Functions 445 • P27/PO7/TIOCB5/(IRQ15)/EDRAK1 Description amended (Before) IRQ5 interrupt input→ (After) IRQ15 interrupt input 445 Note 2 amended Note: 2. IRQ15 input when ITS15 = 1. 10.6.4 Pin Functions 471 • P61/TMRI1/DREQ1/IRQ9 Description amended The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit P61DDR, and bit ITS9 in ITSR.
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Item Page Revision (See Manual for Details) 10.15.4 Pin Functions 515 • PG3/CS3/RAS3/CAS, PG2/CS2/RAS2/RAS Description amended The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, bit CSnE, and bits RMTS2 to RMTS0. 515 • PG1/CS1, PG0/CS0 Description amended The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, and bit CSnE. 10.16.
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Item Page Revision (See Manual for Details) 17.4 Operation 769 Description added [2] Set the DAOE0 bit ... The output value is expressed by the following formula: DADR contents × Vref 256 19.12 Usage Notes 804 Figure 19.12 amended Figure 19.
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Item Page Revision (See Manual for Details) 21.2.1 Connecting a Crystal Resonator 814 Description amended 21.2.2 External Clock Input 815 24.6 Flash Memory Characteristics 907, 908 ... shown in table 21.2. When a crystal resonator is used, the range of its frequencies is from 8 to 25 MHz. Description amended ... for the external clock. When an external clock is used, the range of its frequencies is from 8 to 25 MHz. Table 24.13 Flash Memory Characteristics Table 24.
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Rev. 3.
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Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1 Features ............................................................................................................................. 1 Block Diagram .................................................................................................................. 3 Pin Description............................................................................
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2.8 2.9 2.7.8 Memory Indirect—@@aa:8 ................................................................................ 2.7.9 Effective Address Calculation ............................................................................. Processing States............................................................................................................... Usage Note........................................................................................................................ 2.9.
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Section 5 Interrupt Controller .......................................................................................... 85 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions .....................................................................
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6.4 6.5 6.6 6.7 6.3.7 Bus Control Register (BCR) ................................................................................ 6.3.8 DRAM Control Register (DRAMCR) ................................................................. 6.3.9 DRAM Access Control Register (DRACCR) ...................................................... 6.3.10 Refresh Control Register (REFCR) ..................................................................... 6.3.11 Refresh Timer Counter (RTCNT)..............................
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6.7.9 6.7.10 6.7.11 6.7.12 6.7.13 6.7.14 6.7.15 6.8 6.9 6.10 6.11 6.12 6.13 6.14 Precharge State Count.......................................................................................... Bus Cycle Control in Write Cycle ....................................................................... Byte Access Control ............................................................................................ Burst Operation................................................................................
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7.4 7.5 7.6 7.7 7.3.7 DMA Terminal Control Register (DMATCR)..................................................... Activation Sources ............................................................................................................ 7.4.1 Activation by Internal Interrupt Request.............................................................. 7.4.2 Activation by External Request ........................................................................... 7.4.3 Activation by Auto-Request.............
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8.4 8.5 8.6 8.3.4 EXDMA Mode Control Register (EDMDR) ....................................................... 8.3.5 EXDMA Address Control Register (EDACR) .................................................... Operation .......................................................................................................................... 8.4.1 Transfer Modes .................................................................................................... 8.4.2 Address Modes ...........................
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9.5.3 Block Transfer Mode ........................................................................................... 9.5.4 Chain Transfer ..................................................................................................... 9.5.5 Interrupt Sources.................................................................................................. 9.5.6 Operation Timing................................................................................................. 9.5.
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10.6 10.7 10.8 10.9 10.10 10.11 10.5.2 Port 5 Data Register (P5DR)................................................................................ 10.5.3 Port 5 Register (PORT5)...................................................................................... 10.5.4 Pin Functions ....................................................................................................... Port 6...............................................................................................................
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10.12 Port D................................................................................................................................ 10.12.1 Port D Data Direction Register (PDDDR) ........................................................... 10.12.2 Port D Data Register (PDDR) .............................................................................. 10.12.3 Port D Register (PORTD) .................................................................................... 10.12.
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11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.3.7 Timer General Register (TGR) ............................................................................ 11.3.8 Timer Start Register (TSTR)................................................................................ 11.3.9 Timer Synchronous Register (TSYR) .................................................................. Operation .......................................................................................................................... 11.
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12.3.5 PPG Output Mode Register (PMR)...................................................................... 12.4 Operation .......................................................................................................................... 12.4.1 Output Timing...................................................................................................... 12.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 12.4.
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13.8.2 13.8.3 13.8.4 13.8.5 13.8.6 13.8.7 Contention between TCNT Write and Increment ................................................ Contention between TCOR Write and Compare Match ...................................... Contention between Compare Matches A and B ................................................. Switching of Internal Clocks and TCNT Operation............................................. Mode Setting with Cascaded Connection ............................................................
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15.4 Operation in Asynchronous Mode .................................................................................... 15.4.1 Data Transfer Format........................................................................................... 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 15.4.3 Clock.................................................................................................................... 15.4.4 SCI Initialization (Asynchronous Mode) ...................
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Section 16 A/D Converter ................................................................................................. 741 16.1 Features ............................................................................................................................. 16.2 Input/Output Pins .............................................................................................................. 16.3 Register Descriptions ....................................................................................
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19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 19.5.
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22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).................... 22.2 Operation .......................................................................................................................... 22.2.1 Clock Division Mode........................................................................................... 22.2.2 Sleep Mode .......................................................................................................... 22.2.3 Software Standby Mode...................
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Figures Section 1 Overview Figure 1.1 H8S/2678 Group Internal Block Diagram ........................................................... Figure 1.2 H8S/2678R Group Internal Block Diagram......................................................... Figure 1.3 H8S/2678 Group Pin Arrangement...................................................................... Figure 1.4 H8S/2678R Group Pin Arrangement ................................................................... 3 4 5 6 Section 2 CPU Figure 2.
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Figure 4.4 Operation when SP Value Is Odd ........................................................................ 83 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller ................................................................ Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ...................................................... Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 ..................................................
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Figure 6.23 Figure 6.24 Figure 6.25 Figure 6.26 Figure 6.27 Figure 6.28 Figure 6.29 Figure 6.30 Figure 6.31 Figure 6.32 Figure 6.33 Figure 6.34 Figure 6.35 Figure 6.36 Figure 6.37 Figure 6.38 Figure 6.39 Figure 6.40 Figure 6.41 Figure 6.42 Figure 6.43 Figure 6.44 Figure 6.45 Figure 6.46 Figure 6.47 Figure 6.48 Figure 6.49 Figure 6.50 Figure 6.51 Figure 6.52 Example of Access Timing when RAS Signal Goes Low from Beginning of Tr State (CAST = 0) ...............................................................
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Figure 6.53 Figure 6.54 Figure 6.55 Figure 6.56 Figure 6.57 Figure 6.58 Figure 6.59 Figure 6.60 Figure 6.61 Figure 6.62 Figure 6.63 Figure 6.64 Figure 6.65 Figure 6.66 Figure 6.67 Figure 6.68 Figure 6.69 Figure 6.70 Figure 6.71 Figure 6.72 Figure 6.73 Figure 6.74 Figure 6.75 Figure 6.76 Figure 6.77 Figure 6.78 Figure 6.79 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2) .. 217 Auto Refresh Timing ...........................................................................................
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Figure 6.80 Figure 6.81 Figure 6.82 Figure 6.83 Figure 6.84 Figure 6.85 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) .................. Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode.................................
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Figure 7.29 Figure 7.30 Figure 7.31 Figure 7.32 Figure 7.33 Figure 7.34 Figure 7.35 Figure 7.36 Figure 7.37 Figure 7.38 Figure 7.39 Figure 7.40 Figure 7.41 Example of Single Address Mode Transfer (Word Write) .................................. Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer Example of DREQ Pin Low Level Activated Single Address Mode Transfer .... Example of Dual Address Transfer Using Write Data Buffer Function ..............
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Figure 8.23 Figure 8.24 Figure 8.25 Figure 8.26 Figure 8.27 Figure 8.28 Figure 8.29 Figure 8.30 Figure 8.31 Figure 8.32 Figure 8.33 Figure 8.34 Figure 8.35 Figure 8.36 Figure 8.37 Figure 8.38 Figure 8.39 Figure 8.40 Figure 8.41 Figure 8.42 Figure 8.43 Figure 8.44 Example of Single Address Mode (Word Read) Transfer ................................... Example of Single Address Mode (Byte Write) Transfer.................................... Example of Single Address Mode (Word Write) Transfer .................
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Figure 8.45 Figure 8.46 Transfer End Interrupt Logic ............................................................................... 395 Example of Procedure for Restarting Transfer on Channel in which Transfer End Interrupt Occurred ........................................................................................ 397 Section 9 Data Transfer Controller (DTC) Figure 9.1 Block Diagram of DTC........................................................................................ Figure 9.
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Figure 11.22 Figure 11.23 Figure 11.24 Figure 11.25 Figure 11.26 Figure 11.27 Figure 11.28 Figure 11.29 Figure 11.30 Figure 11.31 Figure 11.32 Figure 11.33 Figure 11.34 Figure 11.35 Figure 11.36 Figure 11.37 Figure 11.38 Figure 11.39 Figure 11.40 Figure 11.41 Figure 11.42 Figure 11.43 Figure 11.44 Figure 11.45 Figure 11.46 Figure 11.47 Figure 11.48 Figure 11.49 Figure 11.50 Figure 11.51 Figure 11.52 Figure 11.53 Example of PWM Mode Operation (2)..............................................................
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Figure 12.8 Figure 12.9 Figure 12.10 Figure 12.11 Setup Procedure for Non-Overlapping Pulse Output (Example) ......................... Non-Overlapping Pulse Output Example (Four-Phase Complementary) ............ Inverted Pulse Output (Example)......................................................................... Pulse Output Triggered by Input Capture (Example) .......................................... 621 622 624 625 Section 13 8-Bit Timers (TMR) Figure 13.1 Block Diagram of 8-Bit Timer Module .....
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Figure 15.9 Sample Serial Reception Data Flowchart (2)....................................................... Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)......................................... Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart....................................... Figure 15.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................
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Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 External Trigger Input Timing............................................................................. A/D Conversion Accuracy Definitions ................................................................ A/D Conversion Accuracy Definitions ................................................................ Example of Analog Input Circuit.........................................................................
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Section 22 Power-Down Modes Figure 22.1 Mode Transitions ................................................................................................. 821 Figure 22.2 Software Standby Mode Application Example.................................................... 829 Figure 22.3 Hardware Standby Mode Timing......................................................................... 830 Section 24 Electrical Characteristics Figure 24.1 Output Load Circuit .......................................................
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Figure 24.35 Figure 24.36 Figure 24.37 Figure 24.38 Figure 24.39 Figure 24.40 Figure 24.41 Figure 24.42 Figure 24.43 Figure 24.44 PPG Output Timing ............................................................................................. TPU Input/Output Timing.................................................................................... TPU Clock Input Timing ..................................................................................... 8-Bit Timer Output Timing...........................
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Tables Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode ............................................................ 7 Table 1.2 Pin Functions.......................................................................................................... 13 Section 2 CPU Table 2.1 Instruction Classification........................................................................................ Table 2.2 Operation Notation..........................................................................
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Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration ................................................................................................... Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ........................................ Table 6.3 Data Buses Used and Valid Strobes ....................................................................... Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space............. Table 6.
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Table 9.4 Table 9.5 Table 9.6 Table 9.7 Register Function in Repeat Mode ......................................................................... Register Function in Block Transfer Mode ............................................................ DTC Execution Status ............................................................................................ Number of States Required for Each Execution Status .......................................... 413 414 418 419 Section 10 I/O Ports Table 10.
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Table 11.28 Table 11.29 Table 11.30 Table 11.31 Table 11.32 Table 11.33 Table 11.34 Table 11.35 Table 11.36 Register Combinations in Buffer Operation........................................................... Cascaded Combinations ......................................................................................... PWM Output Registers and Output Pins................................................................ Clock Input Pins in Phase Counting Mode..................................................
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Table 15.12 Settings of Bits IrCKS2 to IrCKS0 ........................................................................ 732 Table 15.13 SCI Interrupt Sources ............................................................................................. 734 Table 15.14 SCI Interrupt Sources ............................................................................................. 734 Section 16 A/D Converter Table 16.1 A/D Converter Pins ......................................................................
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Table 24.4 Table 24.5 Table 24.6 Table 24.7 Table 24.8 Table 24.9 Table 24.10 Table 24.11 Table 24.12 Table 24.13 Permissible Output Currents .................................................................................. Clock Timing ......................................................................................................... Control Signal Timing............................................................................................ Bus Timing...........................................
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Rev. 3.
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Section 1 Overview Section 1 Overview 1.
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Section 1 Overview • Compact package Product Package (Code) Mounting Height Body Size Pin Pitch H8S/2678 Group QFP-144 FP-144G 3.05 mm (Max.) 22.0 × 22.0 mm 0.5 mm H8S/2678R Group LQFP-144 FP-144H 1.70 mm (Max.) Rev. 3.00 Mar 17, 2006 page 2 of 926 REJ09B0283-0300 22.0 × 22.0 mm 0.
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Section 1 Overview TMR × 2 channels Port 6 PC7/ A7 PC6/ A6 PC5/ A5 PC4/ A4 PC3/ A3 PC2/ A2 PC1/ A1 PC0/ A0 P35/ SCK1/(OE) P34/ SCK0 P33/ RxD1 P32/ RxD0/IrRxD P31/ TxD1 P30/ TxD0/IrTxD P57/ AN15/DA3/IRQ7 P56/ AN14/DA2/IRQ6 P55/ AN13/IRQ5 P54/ AN12/IRQ4 P53/ ADTRG//IRQ3 P52/ SCK2/IRQ2 P51/ RxD2/IRQ1 P50/ TxD2/IRQ0 WDT SCI × 3 channels TPU × 6 channels 8-bit D/A converter PPG Port 7 Port H PH3/CS7/OE/(IRQ7) PH2/CS6/(IRQ6) PH1/CS5 PH0/CS4 P20 /PO0/ TIOCA3/(IRQ8) P21 /PO1/ TIOCB3/(IRQ9) P22 /PO2 /TIOC
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Port A Port B Port C PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1/(OE)/(CKE) P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P57/AN15/DA3/IRQ7 P56/AN14/DA2/IRQ6 P55/AN13/IRQ5 P54/AN12/IRQ4 P53/ADTRG//IRQ3 P52/SCK2/IRQ2 P51/RxD2/IRQ1 P50/TxD2/IRQ0 EXDMAC RAM WDT TMR × 2 channels TPU × 6 channels SCI × 3 channels 8-bit D/A converter PPG Port 4 Port 7 Port H P75 /EDACK1/(DACK1) P74 / EDACK0/(DACK0) P73 / ETEND1/(TEND1) P72 / ETEND0/(TEND0) P71 / EDREQ1/(DREQ1) P70 / EDRE
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1.3.
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109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 FP-144H (Top view) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 MD2 P83 /ETEND3/(IRQ3) P84/EDACK2/(IRQ4) P85/EDACK3/(IRQ5) Vcc PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 Vss PC6/A6 PC7/A7 PB0/A8 PB1/A9 P
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Section 1 Overview 1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin Name Mode 7 Flash Memory Programmer Mode Pin No.
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Section 1 Overview Pin Name Mode 7 Flash Memory Programmer Mode Pin No.
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Section 1 Overview Pin Name Mode 7 Pin No.
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Section 1 Overview Pin Name Pin No.
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Section 1 Overview Pin Name Pin No.
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Section 1 Overview Pin Name Pin No.
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Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) Type Symbol Power supply VCC 5, 39, 67, 96, 116 VSS Clock Operating mode control Input For connection to the power supply. All VCC pins should be connected to the system power supply. 12, 19, 26, 12, 19, 26, 47, 76, 99, 47, 76, 99, 136 136 Input For connection to ground. All VSS pins should be connected to the system power supply (0 V).
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Section 1 Overview Pin No. Type Symbol Operating mode control DCTL FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) — 132 Input Function When this pin is driven high, SDRAMφ dedicated to the synchronous DRAM is output. When not using the synchronous DRAM interface, drive this pin low. The level of this pin must not be changed during operation. RES 93 93 Input When this pin is driven low, the chip is reset.
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Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) Type Symbol Function Bus control RD 90 90 Output When this pin is low, it indicates that the external address space is being read. HWR 89 89 Output Strobe signal indicating that external address space is to be written, and the upper half (D15 to D8) of the data bus is enabled. Write enable signal for DRAM interface space.
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Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) Type Symbol Function Bus control CAS — 104 Output Column address strobe signal for the synchronous DRAM of the synchronous DRAM interface. WE — 105 Output Write enable signal for the synchronous DRAM of the synchronous DRAM interface. WAIT 85 85 Input OE (OE) 112, 133 112, 133 Output Output enable signal for DRAM interface space.
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Section 1 Overview Pin No. Type Symbol FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) Function DMA controller TEND1 82, 81, (DMAC) TEND0 40, 36 (TEND1) (TEND0) 82, 81, 40, 36 DACK1 84, 83, DACK0 42, 41 (DACK1) (DACK0) 84, 83, 42, 41 EDREQ3 141, 140, to 35, 34 EDREQ0 141, 140, 35, 34 Input ETEND3 2, 142, to 40, 36 ETEND0 2, 142, 40, 36 Output These signals indicate the end of EXDMAC data transfer.
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Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) Type Symbol Function 16-bit timer pulse unit (TPU) TIOCA2 TIOCB2 50, 51 50, 51 Input/ output TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. TIOCA3 TIOCB3 TIOCC3 TIOCD3 52, 53, 54, 55 52, 53, 54, 55 Input/ output TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins.
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Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) Type Symbol A/D converter AN15 to AN12, AN7 to AN0 130 to 127, 130 to 127, 126 to 123, 126 to 123, 120 to 117 120 to 117 Input Analog input pins for the A/D converter. ADTRG 110 110 Input Pin for input of an external trigger to start A/D conversion. DA3 to DA0 130, 129, 126, 125 130, 129, 126, 125 Output Analog input pins for the D/A converter.
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Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) Type Symbol I/O ports P57 to P54 130 to 127 130 to 127 Input Four input pins. P53 to P50 110 to 107 110 to 107 Input/ output Four input/output pins. P65 to P60 84 to 81, 61, 60 84 to 81, 61, 60 Input/ output Six input/output pins. P75 to P70 42 to 40, 36 to 34 42 to 40, 36 to 34 Input/ output Six input/output pins. P85 to P80 4 to 2, 4 to 2, 142 to 140 142 to 140 Input/ output Six input/output pins.
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Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.
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Section 2 CPU 16 × 16-bit register-register multiply: 4 states 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes Normal mode* Advanced mode • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
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Section 2 CPU • More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. • Address Space The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space.
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Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP Reserved*1 *3 (SP*2 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used, it is not stored on the stack. 2. SP when EXR is not used. 3.
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Section 2 CPU 2.2.2 Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used.
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Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. Note: Normal mode is not available in this LSI.
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Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC).
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Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
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Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.3 Extended Register (EXR) EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC instructions.
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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
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Section 2 CPU Bit Bit Name Initial Value R/W Description 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise.
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Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers.
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Section 2 CPU Data Type Register Number Word data Rn Data Format 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 3.
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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
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Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.
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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
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Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
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Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
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Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
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Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
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Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
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Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the contents of a general register or memory, or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
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Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.6.
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Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) 2.
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Section 2 CPU Table 2.11 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment Register indirect with pre-decrement @ERn+ @–ERn 5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 2.7.
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Section 2 CPU 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn Register indirect with post-increment—@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction.
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Section 2 CPU 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.
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Section 2 CPU Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* (a) Advanced Mode Note: * Normal mode is not available in this LSI. Figure 2.12 Branch Address Specification in Memory Indirect Mode Rev. 3.
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Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct (Rn) rm Operand is general register contents.
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Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
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Section 2 CPU 2.8 Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset State The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
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Section 2 CPU End of bus request Bus request d En En d of Re ex qu ce es pt tf ion or ha ex nd ce lin pt g ion ha nd lin g que t re up terr =0 BY SS EEP tion SL truc ins Bus-released state ion = 1 ruct BY nst SS EP i E SL of bu s re Bu qu sr es eq t ue st Program execution state Sleep mode st In Exception handling state External interrupt request Software standby mode RES = High STBY = High, RES = Low *1 Reset state Reset state Hardware standby mode*2 Power down state*3 Notes: 1.
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Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2678 Group has twelve operating modes (modes 1, 2, 4 to 7, and 10 to 15). All operating modes are available for the flash memory version. Modes 1, 2, and 4 to 7 are available in the masked ROM version. Modes 1 and 2 are available in the ROMless version. The H8S/2678R Group has seven operating modes (modes 1 to 7). All operating modes are available for the flash memory version.
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Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection MCU Operating Mode*1 FWE*2 MD2 MD1 CPU Operating MD0 Mode 1 0 0 0 1 Advanced 2 0 0 1 0 Advanced 3 — 0 1 1 4 0 1 0 0 5 0 1 0 6 0 1 1 External Data Bus On-Chip ROM Initial Width Max.
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Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of the H8S/2678 Group chip. Bit Bit Name Initial Value R/W Descriptions 7 to 3 — All 0 — Reserved 2 1 0 MDS2 MDS1 MDS0 Note: These bits are always read as 0 and cannot be modified. * 3.2.2 —* —* —* R R R Mode Select 2 to 0 These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0.
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Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Descriptions 3 FLSHE 0 R/W Flash Memory Control Register Enable Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). If this bit is set to 1, the flash memory control registers can be read/written to. If this bit is cleared to 0, the flash memory control registers are not selected. At this time, the contents of the flash memory control registers are maintained.
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Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H carry bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access is designated for all areas by the bus controller, the bus mode switches to 8 bits. 3.3.
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Section 3 MCU Operating Modes 3.3.5 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in an external ROM connected to the first half of area 0 is executed. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H carry bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas.
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Section 3 MCU Operating Modes 3.3.8 Mode 10 This is flash memory boot mode. This mode is the same as mode 4, except for accessing to the flash memory. Mode 10 is available only in the flash memory version of the H8S/2678 Group. 3.3.9 Mode 11 This is flash memory boot mode. This mode is the same as mode 7, except for accessing to the flash memory. Mode 11 is available only in the flash memory version of the H8S/2678 Group. 3.3.10 Mode 12 This is flash memory user program mode.
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Section 3 MCU Operating Modes Table 3.
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Section 3 MCU Operating Modes 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.6 show memory maps for each product.
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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 8 kbytes Modes 5 and 6 (external ROM activation expanded modes with on-chip ROM enabled) H'000000 ROM: 256 kbytes RAM: 8 kbytes Mode 7 (single-chip activation expanded mode with on-chip ROM enabled) H'000000 On-chip ROM External address space H'040000 H'100000 External address space/reserved area*2 On-chip ROM H'140000 External address space H'FFA000 H'FFA000 On-chip RAM/external address space*1 On-chip RAM/external address space*3 H'FFC000 Exter
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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 8 kbytes Mode 10 Boot mode (expanded mode with on-chip ROM enabled) H'000000 ROM: 256 kbytes RAM: 8 kbytes Mode 11 Boot mode (single-chip activation expanded mode with on-chip ROM enabled) H'000000 On-chip ROM On-chip ROM H'040000 H'040000 External address space/reserved area*1 External address space H'FFA000 H'FFA000 On-chip RAM*2 On-chip RAM*2 H'FFC000 External address space H'FFC000 H'FFFC00 H'FFFC00 Internal I/O registers H'FFFF00 Exte
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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 8 kbytes Mode 12 User program mode (expanded mode with on-chip ROM enabled) H'000000 ROM: 256 kbytes RAM: 8 kbytes Modes 13 and 14 User program mode (external ROM activation expanded modes with on-chip ROM enabled) ROM: 256 kbytes RAM: 8 kbytes Mode 15 User program mode (single-chip activation expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM On-chip ROM External address space H'040000 H'040000 H'100000 External address space
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Section 3 MCU Operating Modes RAM: 8 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 ROM: 128 kbytes RAM: 8 kbytes Mode 4 (expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'020000 External address space H'FFA000 H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 External address space Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF On-chip RAM/external address space* H'FFC000 E
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Section 3 MCU Operating Modes ROM: 128 kbytes RAM: 8 kbytes Modes 5 and 6 (external ROM activation expanded modes with on-chip ROM enabled) H'000000 ROM: 128 kbytes RAM: 8 kbytes Mode 7 (single-chip activation expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'020000 External address space External address space/reserved area*2 H'100000 On-chip ROM H'120000 External address space H'FFA000 H'FFA000 On-chip RAM/external address space*1 On-chip RAM/external address space*3 H'FFC000 Exter
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Section 3 MCU Operating Modes RAM: 8 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 ROM: 64 kbytes RAM: 8 kbytes Mode 4 (expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 External address space H'FFA000 H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 External address space Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF On-chip RAM/external address space* H'FFC000 E
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Section 3 MCU Operating Modes ROM: 64 kbytes RAM: 8 kbytes Modes 5 and 6 (external ROM activation expanded modes with on-chip ROM enabled) H'000000 ROM: 64 kbytes RAM: 8 kbytes Mode 7 (single-chip activation expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 External address space H'100000 External address space/reserved area*2 On-chip ROM H'110000 External address space H'FFA000 H'FFA000 On-chip RAM/external address space*1 On-chip RAM/external address space*3 H'FFC000 Exter
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Section 3 MCU Operating Modes RAM: 8 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 External address space H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. Figure 3.4 H8S/2670 Memory Map Rev. 3.
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Section 3 MCU Operating Modes RAM: 32 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 External address space H'FF4000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. Figure 3.5 H8S/2674R Memory Map Rev. 3.
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Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode.
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Section 4 Exception Handling Table 4.
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Section 4 Exception Handling Vector Address* Vector Number Normal Mode* Advanced Mode IRQ13 29 H'003A to H'003B H'0074 to H'0077 IRQ14 30 H'003C to H'003D H'0078 to H'007B IRQ15 31 H'003E to H'003F H'007C to H'007F 32  99 H'0040 to H'0041  H'00C6 to H'00C7 H'0080 to H'0083  H'018C to H'018F Exception Source External interrupt 3 Internal interrupt* 1 2 Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. For details of internal interrupt vectors, see section 5.
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Section 4 Exception Handling Vector fetch Prefetch of first Internal processing program instruction (1) (3) φ RES Internal address bus (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.
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Section 4 Exception Handling Internal processing Vector fetch * * Prefetch of first program instruction * φ RES Address bus (1) (3) (5) RD HWR, LWR D15 to D0 High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted. Figure 4.
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Section 4 Exception Handling Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated.
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Section 4 Exception Handling The interrupt exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. 4.
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Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes*2 SP EXR Reserved*1 SP CCR CCR CCR*1 CCR*1 PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) Interrupt control mode 0 CCR PC (24 bits) Interrupt control mode 2 Notes: 1. Ignored on return. 2.
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Section 4 Exception Handling 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.
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Section 4 Exception Handling Rev. 3.
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Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times.
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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1.
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Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt IRQ15 to IRQ0 Input Rising or falling edge can be selected. Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected. 5.3 Register Descriptions The interrupt controller has the following registers.
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Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W Description 7, 6 — All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 5 4 INTM1 INTM0 0 0 R/W R/W Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller.
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Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 15 — 0 — Reserved This bit is always read as 0 and cannot be modified. 14 13 12 IPR14 IPR13 IPR12 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source.
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Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 6 5 4 IPR6 IPR5 IPR4 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 3 — 0 — Reserved This bit is always read as 0 and cannot be modified.
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Section 5 Interrupt Controller 5.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value R/W Description 15 IRQ15E 0 R/W IRQ15 Enable The IRQ15 interrupt request is enabled when this bit is 1. 14 IRQ14E 0 R/W IRQ14 Enable The IRQ14 interrupt request is enabled when this bit is 1. 13 IRQ13E 0 R/W IRQ13 Enable The IRQ13 interrupt request is enabled when this bit is 1.
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Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 5 IRQ5E 0 R/W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. 4 IRQ4E 0 R/W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 IRQ2E 0 R/W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1.
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Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 13 12 IRQ14SCB IRQ14SCA 0 0 R/W R/W IRQ14 Sense Control B IRQ14 Sense Control A 00: Interrupt request generated at IRQ14 input low level 01: Interrupt request generated at falling edge of IRQ14 input 10: Interrupt request generated at rising edge of IRQ14 input 11: Interrupt request generated at both falling and rising edges of IRQ14 input 11 10 IRQ13SCB IRQ13SCA 0 0 R/W R/W IRQ13 Sense Control B IRQ13 Sense Control A 00
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Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 7 6 IRQ11SCB IRQ11SCA 0 0 R/W R/W IRQ11 Sense Control B IRQ11 Sense Control A 00: Interrupt request generated at IRQ11 input low level 01: Interrupt request generated at falling edge of IRQ11 input 10: Interrupt request generated at rising edge of IRQ11 input 11: Interrupt request generated at both falling and rising edges of IRQ11 input 5 4 IRQ10SCB IRQ10SCA 0 0 R/W R/W IRQ10 Sense Control B IRQ10 Sense Control A 00: In
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Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 1 0 IRQ8SCB IRQ8SCA 0 0 R/W R/W IRQ8 Sense Control B IRQ8 Sense Control A 00: Interrupt request generated at IRQ8 input low level 01: Interrupt request generated at falling edge of IRQ8 input 10: Interrupt request generated at rising edge of IRQ8 input 11: Interrupt request generated at both falling and rising edges of IRQ8 input • ISCRL Bit Bit Name Initial Value R/W Description 15 14 IRQ7SCB IRQ7SCA 0 0 R/W R/W IR
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Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 11 10 IRQ5SCB IRQ5SCA 0 0 R/W R/W IRQ5 Sense Control B IRQ5 Sense Control A 00: Interrupt request generated at IRQ5 input low level 01: Interrupt request generated at falling edge of IRQ5 input 10: Interrupt request generated at rising edge of IRQ5 input 11: Interrupt request generated at both falling and rising edges of IRQ5 input 9 8 IRQ4SCB IRQ4SCA 0 0 R/W R/W IRQ4 Sense Control B IRQ4 Sense Control A 00: Interrupt re
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Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 5 4 IRQ2SCB IRQ2SCA 0 0 R/W R/W IRQ2 Sense Control B IRQ2 Sense Control A 00: Interrupt request generated at IRQ2 input low level 01: Interrupt request generated at falling edge of IRQ2 input 10: Interrupt request generated at rising edge of IRQ2 input 11: Interrupt request generated at both falling and rising edges of IRQ2 input 3 2 IRQ1SCB IRQ1SCA 0 0 R/W R/W IRQ1 Sense Control B IRQ1 Sense Control A 00: Interrupt requ
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Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register.
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Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 13 ITS13 0 R/W Selects IRQ13 input pin. 0: P65 1: P25 12 ITS12 0 R/W Selects IRQ12 input pin. 0: P64 1: P24 11 ITS11 0 R/W Selects IRQ11 input pin. 0: P63 1: P23 10 ITS10 0 R/W Selects IRQ10 input pin. 0: P62 1: P22 9 ITS9 0 R/W Selects IRQ9 input pin. 0: P61 1: P21 8 ITS8 0 R/W Selects IRQ8 input pin. 0: P60 1: P20 7 ITS7 0 R/W Selects IRQ7 input pin.
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Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 ITS3 0 R/W Selects IRQ3 input pin. 0: P53 1: P83 2 ITS2 0 R/W Selects IRQ2 input pin. 0: P52 1: P82 1 ITS1 0 R/W Selects IRQ1 input pin. 0: P51 1: P81 0 ITS0 0 R/W Selects IRQ0 input pin. 0: P50 1: P80 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state.
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Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to restore the chip from software standby mode. NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
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Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/ level detection circuit IRQn input S Q IRQn interrupt request R Clear signal Note: n = 15 to 0 Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 5.4.
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Section 5 Interrupt Controller Table 5.
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Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source TPU_0 TGI0A TGI0B TGI0C — TPU_1 TPU_2 TPU_3 — TPU_4 Vector Address* Advanced Mode IPR Priority 40 H'00A0 IPRF6 to IPRF4 High 41 H'00A4 — 42 H'00A8 — TGI0D 43 H'00AC — TCI0V 44 H'00B0 Reserved for system use 45 H'00B4 46 H'00B8 47 H'00BC TGI1A 48 H'00C0 TGI1B 49 H'00C4 TCI1V 50 H'00C8 — — TCI1U 51 H'00CC — — TGI2A 52 H'00D0 TGI2B 53 H'00D4 TCI2V 54 H'00D8 Vector Number IP
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Section 5 Interrupt Controller Vector Address* Interrupt Source Origin of Interrupt Source TPU_5 TGI5A TGI5B TCI5V 70 H'0118 — — TCI5U 71 H'011C — — CMIA0 72 H'0120 CMIB0 73 H'0124 OVI0 74 H'0128 — — — — TMR_0 Advanced Mode IPR Priority 68 H'0110 IPRG2 to IPRG0 High 69 H'0114 Vector Number DTC DMAC Activation Activation — — IPRH14 to IPRH12 — — Reserved for system use 75 H'012C TMR_1 CMIA1 76 H'0130 CMIB1 77 H'0134 OVI1 78 H'0138 — — Reserved for sy
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Section 5 Interrupt Controller Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC DMAC Activation Activation SCI_2 ERI2 96 H'0180 IPRJ10 to IPRJ8 High — RXI2 97 H'0184 — TXI2 98 H'0188 — TEI2 99 H'018C Reserved for system use 100 H'0190 101 102 — — Reserved for system use — — — — — H'0194 — — H'0198 — — 103 H'019C — — 104 H'01A0 — — 105 H'01A4 — — 106 H'01A8 — — 107 H'01AC — — 108 H'01B0 —
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Section 5 Interrupt Controller Interrupt Source — Origin of Interrupt Source Reserved for system use Vector Address* Vector Number Advanced Mode IPR Priority DTC DMAC Activation Activation 120 H'01E0 IPRK2 to IPRK0 High — — 121 H'01E4 — — 122 H'01E8 — — 123 H'01EC — — 124 H'01F0 — — 125 H'01F4 — — 126 H'01F8 — — — — 127 Note: * 5.6 Low H'01EC Lower 16 bits of the start address.
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Section 5 Interrupt Controller 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit of CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending.
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Section 5 Interrupt Controller Program execution status No Interrupt generated? Yes Yes NMI No I=0 No Hold pending Yes No IRQ0 Yes No IRQ1 Yes TEI_2 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 3.
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Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2.
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Section 5 Interrupt Controller Program execution status No Interrupt generated? Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes No Level 6 interrupt? No Yes Level 1 interrupt? No Mask level 5 or below? No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 3.
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Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 3.
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(1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
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Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.
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Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8-Bit Bus Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK 16-Bit Bus Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access 1 4 6+2m 2 3+m Legend: m: Number of wait states in an external device access 5.6.5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt.
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Section 5 Interrupt Controller Interrupt request IRQ interrupt On-chip supporting module Interrupt source clear signal Clear signal Disable signal DMAC DTC activation request vector number Selection circuit Select signal Clear signal DTCER Control logic DTC Clear signal DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, I2 to I0 Interrupt controller Figure 5.
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Section 5 Interrupt Controller (3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or CPU interrupt factor, these operate independently. Table 5.
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Section 5 Interrupt Controller priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in the TPU’s TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
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Section 5 Interrupt Controller 5.7.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle.
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Section 5 Interrupt Controller Rev. 3.
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Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus mastership—the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC), and data transfer controller (DTC). 6.
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Section 6 Bus Controller (BSC) A block diagram of the bus controller is shown in figure 6.1.
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Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that basic bus interface space is accessed and address output on address bus is enabled. Read RD Output Strobe signal indicating that basic bus interface space is being read.
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Section 6 Bus Controller (BSC) Name Symbol I/O Chip select 5/row address strobe 5/SDRAMφ* Output CS5/ RAS5/* SDRAMφ* Strobe signal indicating that area 5 is selected, DRAM row address strobe signal when area 5 is DRAM interface space, or dedicated clock signal for the synchronous DRAM when the synchronous DRAM interface is selected. Chip select 6 CS6 Output Strobe signal indicating that area 6 is selected. Chip select 7 CS7 Output Strobe signal indicating that area 7 is selected.
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Section 6 Bus Controller (BSC) Name I/O Function Data transfer acknowledge EDACK1 1 (EXDMAC) Output Data transfer acknowledge signal for single address transfer by EXDMAC channel 1. Data transfer acknowledge EDACK0 0 (EXDMAC) Output Data transfer acknowledge signal for single address transfer by EXDMAC channel 0. Note: 6.3 Symbol * These pins are not supported in the H8S/2678 Group. Register Descriptions The bus controller has the following registers.
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Section 6 Bus Controller (BSC) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Bit Name Initial Value* R/W Description 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 R/W R/W R/W R/W R/W R/W R/W R/W Area 7 to 0 Bus Width Control Note: * 6.3.
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Section 6 Bus Controller (BSC) 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a synchronous DRAM is connected. • WTCRAH Bit Bit Name Initial Value R/W Description 15 — 0 R Reserved This bit is always read as 0 and cannot be modified.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 9 8 W62 W61 W60 1 1 1 R/W R/W R/W Area 6 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 1 0 W42 W41 W40 1 1 1 R/W R/W R/W Area 4 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 4 while AST4 bit in ASTCR = 1.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 9 8 W22 W21 W20 1 1 1 R/W R/W R/W Area 2 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. A CAS latency is set when the synchronous DRAM is connected*. The setting of area 2 is reflected to the setting of areas 2 to 5. A CAS latency can be set regardless of whether or not an ASTCR wait state insertion is enabled.
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Section 6 Bus Controller (BSC) • WTCRBL Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0 and cannot be modified. 6 5 4 W12 W11 W10 1 1 1 R/W R/W R/W Area 1 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1.
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Section 6 Bus Controller (BSC) 6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read Strobe Timing Control 7 to 0 These bits set the negation timing of the read strobe in a corresponding area read access. As shown in figure 6.
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Section 6 Bus Controller (BSC) 6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL) CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended. Extending the assertion period of the CSn and address signals allows flexible interfacing to external I/O devices.
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Section 6 Bus Controller (BSC) Bus cycle Th T1 T2 T3 Tt Address CS RD Read Data HWR, LWR Write Data Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Rev. 3.
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Section 6 Bus Controller (BSC) 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively. Bit Bit Name Initial Value R/W Description 7 BSRMn 0 R/W Burst ROM Interface Select Selects the basic bus interface or burst ROM interface.
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Section 6 Bus Controller (BSC) 6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Bit Bit Name Initial Value R/W Description 15 BRLE 0 R/W External Bus Release Enable Enables or disables external bus release.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 ICIS0 1 R/W Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 9 WDBE 0 R/W Write Data Buffer Enable The write data buffer function can be used for an external write cycle or DMAC single address transfer cycle.
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Section 6 Bus Controller (BSC) 6.3.8 DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM* interface settings. Note: * The synchronous DRAM interface is not supported in the H8S/2678 Group. Bit Bit Name Initial Value R/W Description 15 OEE 0 R/W OE Output Enable The OE signal used when EDO page mode DRAM is connected can be output from the (OE) pin. The OE signal is common to all areas designated as DRAM space.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 12 CAST 0 R/W Column Address Output Cycle Number Select Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. 0: 2 states 1: 3 states 11 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 7 BE 0 R/W Burst Access Enable Selects enabling or disabling of burst access to areas designated as DRAM/continuous synchronous DRAM space. DRAM/continuous synchronous DRAM space burst access is performed in fast page mode. When using EDO page mode DRAM, the OE signal must be connected.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 5 DDS 0 R/W DMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when DMAC single address transfer is performed on the DRAM/synchronous DRAM interface. When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, DMAC single address transfer is performed in full access mode regardless of the setting of this bit.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 1 0 MXC2 MXC1 MXC0 0 0 0 R/W R/W R/W Address Multiplex Select These bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM/synchronous DRAM interface, these bits also select the row address bits to be used for comparison.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 011: 11-bit shift • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM interface 100: 8-bit shift • When 8-bit access space is designated: Row address bits A23 to A8 used for comparison • When 16-bit access space is designated: Row address bits A23 to A9 used for comparison The precharge
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 111: 11-bit shift • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison • When 16-bit access space is designated: Row address bits A23 to A12 used for comparison The precharge-sel is A15 to A12 of the column address. Bus cycle Tp Tr Row address Address Tc1 Tc2 Column address RAST = 0 RAS RAST = 1 RAS UCAS, LCAS Figure 6.
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Section 6 Bus Controller (BSC) • H8S/2678 Group Bit Bit Name Initial Value R/W Description 7 DRMI 0 R/W Idle Cycle Insertion An idle cycle can be inserted after a DRAM read cycle when a continuous normal space access cycle follows a DRAM read cycle. Idle cycle insertion conditions, setting of number of states, etc., comply with settings of bits ICIS1, ICIS0, and IDLC in BCR register 0: Idle cycle not inserted 1: Idle cycle inserted 6 — 0 R/W Reserved This bit can be read from or written to.
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Section 6 Bus Controller (BSC) • H8S/2678R Group Bit Bit Name Initial Value R/W Description 15 DRMI 0 R/W Idle Cycle Insertion An idle cycle can be inserted after a DRAM/synchronous DRAM access cycle when a continuous normal space access cycle follows a DRAM/synchronous DRAM access cycle. Idle cycle insertion conditions, setting of number of states, etc.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 9 8 RCD1 RCD0 0 0 R/W R/W RAS-CAS Wait Control These bits select a wait cycle to be inserted between the RAS assert cycle and CAS assert cycle. A 1- to 4-state wait cycle can be inserted. 00: Wait cycle not inserted 01: 1-state wait cycle inserted 10: 2-state wait cycle inserted 11: 3-state wait cycle inserted 7 to 4 — All 0 R/W Reserved These bits can be read from or written to.
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Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ Address bus Column address Precharge-sel Column address Row address Row address RAS SDWCD 0 CAS WE CKE High DQMU, DQML Data bus Address bus PALL ACTV NOP WRIT Tp Tr Tc1 Tc2 Column address Precharge-sel Row address NOP Column address Row address RAS SDWCD 1 CAS WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.
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Section 6 Bus Controller (BSC) 6.3.10 Refresh Control Register (REFCR) REFCR specifies DRAM/synchronous DRAM interface refresh control. Note: The synchronous DRAM interface is not supported in the H8S/2678 Group. Bit 15 Bit Name CMF Initial Value R/W Description 0 R/(W)* Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 11 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 10 9 8 RTCK2 RTCK1 RTCK0 0 0 0 R/W R/W R/W Refresh Counter Clock Select These bits select the clock to be used to increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up.
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 5 4 RLW1 RLW0 0 0 R/W R/W Refresh Cycle Wait Control These bits select the number of wait states to be inserted in a DRAM interface CAS-beforeRAS refresh cycle/synchronous DRAM interface auto-refresh cycle. This setting applies to all areas designated as DRAM/continuous synchronous DRAM space.
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Section 6 Bus Controller (BSC) 6.3.11 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match interrupt (CMI) is generated.
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Section 6 Bus Controller (BSC) H'000000 H'0000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'FFFF H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF (1) Advanced mode (2) Normal mode* Note: * Not available in this LSI Figure 6.6 Area Divisions Rev. 3.
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Section 6 Bus Controller (BSC) 6.4.2 Bus Specifications The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR.
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Section 6 Bus Controller (BSC) Table 6.
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Section 6 Bus Controller (BSC) 6.4.3 Memory Interfaces The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; a synchronous DRAM interface* that allows direct connection of synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area.
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Section 6 Bus Controller (BSC) If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The OE pin is used as the CKE signal. Area 6: In externally expanded mode, all of area 6 is external space. When area 6 external space is accessed, the CS6 signal can be output.
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Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus Area n external address CSn Figure 6.7 CSn Signal Output Timing (n = 0 to 7) 6.5 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
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Section 6 Bus Controller (BSC) Upper data bus D15 Lower data bus D8 D7 D0 Byte size Word size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space: Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses.
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Section 6 Bus Controller (BSC) 6.5.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.
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Section 6 Bus Controller (BSC) Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space Rev. 3.
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Section 6 Bus Controller (BSC) 8-Bit, 3-State Access Space: Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.
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Section 6 Bus Controller (BSC) 16-Bit, 2-State Access Space: Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be inserted. Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2.
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Section 6 Bus Controller (BSC) Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Rev. 3.
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Section 6 Bus Controller (BSC) Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev. 3.
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Section 6 Bus Controller (BSC) 16-Bit, 3-State Access Space: Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2.
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Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Rev. 3.
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Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev. 3.
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Section 6 Bus Controller (BSC) 6.5.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings in WTCRA and WTCRB.
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Section 6 Bus Controller (BSC) By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Notes: 1. Downward arrows indicate the timing of WAIT pin sampling. 2. When RDN = 0 Figure 6.18 Example of Wait State Insertion Timing 6.5.5 Read Strobe (RD RD) RD Timing The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR. Figure 6.
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Section 6 Bus Controller (BSC) Bus cycle T2 T1 T3 φ Address bus CSn AS RD RDNn = 0 Data bus RD RDNn = 1 Data bus DACK, EDACK Figure 6.19 Example of Read Strobe Timing 6.5.6 Extension of Chip Select (CS CS) CS Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR.
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Section 6 Bus Controller (BSC) Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus 3-state access space. Bus cycle Th T1 T2 T3 Tt φ Address bus CSn AS Read (when RDNn = 0) RD Data bus Read data HWR, LWR Write Data bus Write data Figure 6.
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Section 6 Bus Controller (BSC) 6.6 DRAM Interface In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst operation is also possible, using fast page mode. 6.6.1 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR.
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Section 6 Bus Controller (BSC) Table 6.
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Section 6 Bus Controller (BSC) 6.6.4 Pins Used for DRAM Interface Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2 to CS5 pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2 to RAS5 signals are output. Table 6.
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Section 6 Bus Controller (BSC) 6.6.5 Basic Timing Figure 6.21 shows the basic access timing for DRAM space. The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.
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Section 6 Bus Controller (BSC) (OE ) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space, the signal is output only from the RD pin. 6.6.6 Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR.
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Section 6 Bus Controller (BSC) 6.6.7 Row Address Output State Control If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr state, and the row address hold time and DRAM read access time are changed relative to the fall of the RAS signal. Use the optimum setting according to the DRAM connected and the operating frequency of this LSI. Figure 6.23 shows an example of the timing when the RAS signal goes low from the beginning of the Tr state.
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Section 6 Bus Controller (BSC) If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three Trw states, in which row address output is maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which the column address is output.
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Section 6 Bus Controller (BSC) 6.6.8 Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is always inserted when DRAM space is accessed. From one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the DRAM connected and the operating frequency of this LSI. Figure 6.25 shows the timing when two Tp states are inserted.
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Section 6 Bus Controller (BSC) 6.6.9 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access.
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Section 6 Bus Controller (BSC) By program wait Tp Tr Tc1 Tw By WAIT pin Tw φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Notes: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.26 Example of Wait State Insertion Timing (2-State Column Address Output) Rev. 3.
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Section 6 Bus Controller (BSC) Tp Tr By program wait By WAIT pin Tc1 Tw Tw Tc2 Tc3 φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Notes: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.27 Example of Wait State Insertion Timing (3-State Column Address Output) Rev. 3.
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Section 6 Bus Controller (BSC) 6.6.10 Byte Access Control When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.28 shows the control timing for 2-CAS access, and figure 6.29 shows an example of 2-CAS DRAM connection. Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS LCAS High WE (HWR) OE (RD) High Write data Upper data bus High-Z Lower data bus Note: n = 2 to 5 Figure 6.
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Section 6 Bus Controller (BSC) This LSI (Address shift size set to 10 bits) 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration 10-bit column address RASn (CSn) RAS UCAS UCAS LCAS LCAS HWR (WE) RD (OE) A10 WE OE A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 Row address input: A9 to A0 Column address input: A9 to A0 D15 to D0 Figure 6.29 Example of 2-CAS DRAM Connection 6.6.
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Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc1 Tc2 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) Rev. 3.
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Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details see section 6.6.
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Section 6 Bus Controller (BSC)  self-refreshing is performed  the chip enters software standby mode  the external bus is released  the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction.
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Section 6 Bus Controller (BSC) • RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.33 shows an example of the timing in RAS up mode.
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Section 6 Bus Controller (BSC) 6.6.12 Refresh Control This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit to 1 in REFCR.
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Section 6 Bus Controller (BSC) φ RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.35 Compare Match Timing TRp TRr TRc1 TRc2 φ CSn (RASn) UCAS, LCAS Figure 6.36 CBR Refresh Timing A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations. Figure 6.
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Section 6 Bus Controller (BSC) TRp TRrw TRr TRc1 TRc2 φ CSn (RASn) UCAS, LCAS Figure 6.37 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) Depending on the DRAM used, modification of the WE signal may not be permitted during the refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.38 shows an example of the timing when the CBRM bit is set to 1.
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Section 6 Bus Controller (BSC) Normal space access request φ A23 to A0 CS AS RD HWR (WE) Refresh period RAS CAS Figure 6.38 Example of CBR Refresh Timing (CBRM = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR.
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Section 6 Bus Controller (BSC) TRp Software standby TRr TRc3 φ CSn (RASn) UCAS, LCAS HWR (WE) High Note: n = 2 to 5 Figure 6.39 Self-Refresh Timing In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time.
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Section 6 Bus Controller (BSC) Software standby DRAM space write Trc3 Trp1 Trp2 Tp Tr Tc1 Tc2 φ Address bus RASn (CSn) UCAS, LCAS OE (RD) WR (HWR) Data bus Note: n = 2 to 5 Figure 6.
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Section 6 Bus Controller (BSC) or EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed. When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only, irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low from the Tc1 state. Figure 6.41 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or EDDS = 1.
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Section 6 Bus Controller (BSC) When DDS = 0 or EDDS = 0: When DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing DRAM space. Figure 6.42 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or EDDS = 0.
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Section 6 Bus Controller (BSC) 6.7 Synchronous DRAM Interface In the H8S/2678R Group, external address space areas 2 to 5 can be designated as continuous synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Synchronous DRAM of CAS latency 1 to 4 can be connected.
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Section 6 Bus Controller (BSC) Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT), and mode-register write (MRS). Commands for bank control cannot be used. 6.7.2 Address Multiplexing With continuous synchronous DRAM space, the row address and column address are multiplexed.
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Section 6 Bus Controller (BSC) 6.7.3 Data Bus If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space. In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be connected directly.
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Section 6 Bus Controller (BSC) Table 6.
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Section 6 Bus Controller (BSC) 6.7.5 Synchronous DRAM Clock When the DCTL pin is fixed to 1, synchronous clock (SDRAMφ) is output from the CS5 pin. When the frequency multiplication factor of the PLL circuit of this LSI is set to ×1 or ×2, SDRAMφ is 90° phase shift from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between φ and SDRAMφ.
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Section 6 Bus Controller (BSC) Tp Tr Column address Row address Tc1 Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1) Rev. 3.
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Section 6 Bus Controller (BSC) 6.7.7 CAS Latency Control CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency count, as shown in table 6.10, by the setting of synchronous DRAM. Depending on the setting, the CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless of the setting of the AST2 bit of ASTCR. Figure 6.45 shows the CAS latency control timing when synchronous DRAM of CAS latency 3 is connected. The initial value of W22 to W20 is H'7.
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Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl1 Tcl2 Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) Rev. 3.
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Section 6 Bus Controller (BSC) 6.7.8 Row Address Output State Control When the command interval specification from the ACTV command to the next READ/WRIT command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR.
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Section 6 Bus Controller (BSC) Tp Tr Trw Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Column address Row address Row address Precharge-sel RAS CAS Read WE CKE High DQMU, DQML Data bus PALL ACTV NOP READ NOP RAS CAS Write WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP Figure 6.46 Example of Access Timing when Row Address Output Hold State Is 1 State (RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) Rev. 3.
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Section 6 Bus Controller (BSC) 6.7.9 Precharge State Count When the interval specification from the PALL command to the next ACTV/REF command cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.47 shows the timing when two Tp states are inserted. Rev. 3.
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Section 6 Bus Controller (BSC) The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 Tp2 Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Column address Row address Precharge-sel RAS CAS Read WE CKE High DQMU, DQML Data bus PALL NOP ACTV READ NOP RAS CAS Write WE CKE High DQMU, DQML Data bus PALL NOP ACTV NOP WRIT NOP Figure 6.
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Section 6 Bus Controller (BSC) 6.7.10 Bus Cycle Control in Write Cycle By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled. Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to synchronous DRAM read access. Figure 6.48 shows the write access timing when the CAS latency control cycle is disabled.
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Section 6 Bus Controller (BSC) 6.7.11 Byte Access Control When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are used for the control signals needed for byte access. Figures 6.49 and 6.50 show the control timing for DQM, and figure 6.51 shows an example of connection of byte control by DQMU and DQML.
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Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE CKE High DQMU High DQML Upper data bus High-Z Lower data bus PALL ACTV READ NOP Figure 6.50 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) Rev. 3.
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Section 6 Bus Controller (BSC) This LSI (Address shift size set to 8 bits) CS2 (RAS) RAS CS3 (CAS) CAS CS4 (WE) WE UCAS (DQMU) DQMU LCAS (DQML) DQML CS5 (SDRAMø) CLK A23 A13 (BS1) A21 A12 (BS0) A12 A11 A11 A10 A10 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 DCTL 16-Mbit synchronous DRAM 1-Mword × 16 bits × 4-bank configuration 8-bit column address OE (CKE) I/O PORT Row address input: A11 to A0 Column address input: A7 to A0 Bank select ad
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Section 6 Bus Controller (BSC) 6.7.12 Burst Operation With synchronous DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, burst access is also provided which can be used when making consecutive accesses to the same row address. This access enables fast access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRAMCR.
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Section 6 Bus Controller (BSC) Tp Tr Column address 1 Row address Tc1 Tcl Tc2 Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Column address 2 Row address Precharge-sel RAS CAS Read WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP RAS CAS Write WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP WRIT NOP Figure 6.52 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) Rev. 3.
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Section 6 Bus Controller (BSC) RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous synchronous DRAM space is not continuous, but is interrupted by access to another space. In this case, if the row address active state is held during the access to the other space, the read or write command can be issued without ACTV command generation similarly to DRAM RAS down mode. To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings.
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Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 Continuous synchronous DRAM space read Tc1 Tcl Tc2 φ Address bus Column Row address address Precharge-sel Row address Column address External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP Figure 6.53 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2) 6.7.
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Section 6 Bus Controller (BSC) Auto Refreshing: To select auto refreshing, set the RFSHE bit to 1 in REFCR. With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
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Section 6 Bus Controller (BSC) When the interval specification from the PLL command to the REF command cannot be satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be inserted after the TRp cycle that is set by the TPC1 and TPC0 bits of DRACCR. Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.55 shows the timing when one wait state is inserted.
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Section 6 Bus Controller (BSC) When the interval specification from the REF command to the ACTV cannot be satisfied, setting the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh cycle. Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.56 shows the timing when one wait state is inserted.
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Section 6 Bus Controller (BSC) When using self-refresh mode, the OPE bit must not be cleared to 0 in SBYCR. TRp TRr PALL SELF Software standby TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE NOP Figure 6.57 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing self-refreshing and the next command is specified.
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Section 6 Bus Controller (BSC) Continuous synchronous DRAM space write Software standby TRc2 TRp1 TRp2 Tp Tr Column address Row address Tc1 Tcl Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE CKE DQMU, DQML Data bus NOP PALL ACTV NOP NOP NOP Figure 6.
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Section 6 Bus Controller (BSC) 6.7.14 Mode Register Setting of Synchronous DRAM To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After that, access the continuous synchronous DRAM space in bytes.
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Section 6 Bus Controller (BSC) 6.7.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed.
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Section 6 Bus Controller (BSC) Tp Tr Column address Row address Tc1 Tcl Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP DACK or RDACK Figure 6.60 Example of DACK/EDACK DACK EDACK Output Timing when DDS = 1 or EDDS = 1 Rev. 3.
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Section 6 Bus Controller (BSC) When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing continuous synchronous DRAM space. Figure 6.
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Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP DACK or RDACK Figure 6.61 Example of DACK/EDACK DACK EDACK Output Timing when DDS = 0 or EDDS = 0 Rev. 3.
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Section 6 Bus Controller (BSC) (2) Read Data Extension If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is readaccessed in DMAC/EXDMAC single address mode, the establishment time for the read data can be extended by clock suspend mode. The number of states for insertion of the read data extension cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in DRAMCR when the read data will be extended.
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Section 6 Bus Controller (BSC) 6.8 Burst ROM Interface In this LSI, external space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space interface enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the setting of the BSWD11 and BSWD10 bits in BROMCR.
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Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T3 T1 T2 T1 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.63 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Rev. 3.
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Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.64 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.8.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4, Wait Control.
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Section 6 Bus Controller (BSC) 6.9 Idle Cycle 6.9.1 Operation When this LSI accesses external space, it can insert an idle cycle (Ti) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle (in the H8S/2678R Group, it cannot insert an idle cycle in the condition (3)).
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Section 6 Bus Controller (BSC) Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.66 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle.
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Section 6 Bus Controller (BSC) Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T2 T1 φ φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD HWR, LWR HWR Data bus Data bus Long output floating time (a) No idle cycle insertion (ICIS2 = 0) Data collision T2 T3 Bus cycle B Ti T1 T2 Idle cycle (b) Idle cycle insertion (ICIS2 = 1, initial value) Figure 6.
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Section 6 Bus Controller (BSC) Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T2 T1 φ φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD T2 Bus cycle B T3 Overlap period between CS (area B) and RD may occur Ti T1 T2 Idle cycle (b) Idle cycle insertion (ICIS1 = 1, initial value) (a) No idle cycle insertion (ICIS1 = 0) Figure 6.
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Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 External read Tc2 T1 T2 T3 DRAM space read Ti Tc1 Tc2 φ Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) DRAM space read Tp Tr Tc1 External read Tc2 T1 T2 T3 DRAM space write Ti Tc1 Tc2 φ Address bus RD HWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.
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Section 6 Bus Controller (BSC) Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space Access: In a continuous synchronous DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to continuous synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case is shown in figure 6.
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Section 6 Bus Controller (BSC) and 6.74. In write access, DQMU and DQML are not in accordance with the settings of the IDLC bit. The timing in this case is illustrated in figure 6.75.
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Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space read External space read Tc2 T1 T2 T3 Ti Ti Tc1 TCl Tc2 φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ READ NOP NOP Idle cycle Figure 6.
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Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 T3 Continuous synchronous DRAM space write Ti Tc1 TCl Tc2 φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ NOP WRIT NOP Idle cycle Figure 6.
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Section 6 Bus Controller (BSC) When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if bits ICIS1 and ICIS0 are set to 1. DRAM space read Tp Tr Tc1 External read Tc2 Ti T1 T2 DRAM space read T3 Ti Tc1 Tc2 φ Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.76 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) Rev. 3.
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Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 External write Tc2 Ti T1 T2 DRAM space read T3 Tc1 Tc2 φ Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.
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Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 External space read Tc2 Ti T1 T2 DRAM space read T3 Tc1 Tc2 φ Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access (IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) Idle Cycle in Case of Normal Space Access After Continuous Synchronous DRAM Space Access: Note: In the H8S/2678 Group, the synchronous DRAM interface is not supported.
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Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space read External space read Tc2 Ti T1 T2 T3 Ti Tc1 TCl Tc2 φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD Data bus PALL ACTV READ NOP READ NOP Idle cycle Figure 6.
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Section 6 Bus Controller (BSC) Continuous synchronous DRAM space write φ Tp Tr Address bus Row Column address address Precharge-sel Row address Tc1 Tc2 Continuous synchronous DRAM space read External space read Ti Column address T1 T2 External address T3 Tc1 TCl Tc2 Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR Data bus PALL ACTV NOP WRIT NOP READ NOP Idle cycle Figure 6.
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Section 6 Bus Controller (BSC) Table 6.
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Section 6 Bus Controller (BSC) Previous Access Next Access Normal space read DRAM/continuous synchronous DRAM* space write DRAM/continuous synchronous DRAM * space read Note: * ICIS2* ICIS1 ICIS0 DRMI IDLC Idle cycle 0 — — — — Disabled 1 — — — 0 — — — 1 — — — 0 1 state inserted 1 2 states inserted — Disabled 0 1 state inserted 1 2 states inserted In the H8S/2678 Group, the synchronous DRAM interface is not supported.
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Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space write Tc2 Ti Tc1 Tc2 φ Address bus Column Row address address Column address External address Precharge-sel RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP WRIT Idle cycle Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode (SDWCD = 1, CAS Latency 2) Rev.
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Section 6 Bus Controller (BSC) 6.9.2 Pin States in Idle Cycle Table 6.12 shows the pin states in an idle cycle. Table 6.12 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 CSn (n = 7 to 0) High impedance 1 2 High* * UCAS, LCAS High* AS High RD High (OE) High HWR, LWR High DACKn (n = 1, 0) High EDACKn (n = 3 to 0) High 2 Notes: 1. Remains low in DRAM space RAS down mode. 2. Remains low in a DRAM space refresh cycle. 6.
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Section 6 Bus Controller (BSC) On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 φ Internal address bus Internal memory Internal I/O register address Internal read signal A23 to A0 External address CSn External space write HWR, LWR D15 to D0 Figure 6.83 Example of Timing when Write Data Buffer Function is Used 6.11 Bus Release This LSI can release the external bus in response to a bus request from an external device.
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Section 6 Bus Controller (BSC) 6.11.1 Operation In externally expanded mode, the bus can be released to an external device by setting the BRLE bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state.
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Section 6 Bus Controller (BSC) 6.11.2 Pin States in External Bus Released State Table 6.13 shows pin states in the external bus released state. Table 6.13 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance CSn (n = 7 to 0) High impedance UCAS, LCAS High impedance AS High impedance RD High impedance (OE) High impedance HWR, LWR High impedance DACKn (n = 1, 0) High EDACKn (n = 3 to 0) High Rev. 3.
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Section 6 Bus Controller (BSC) 6.11.3 Transition Timing Figure 6.84 shows the timing for transition to the bus released state. External space access cycle CPU cycle External bus released state T1 T2 φ High-Z Address bus High-Z Data bus High-Z AS High-Z RD High-Z HWR, LWR BREQ BACK BREQO [1] [2] [3] [4] [5] [6] [7] [8] [1] Low level of BREQ signal is sampled at rise of ø. [2] Bus control signal returns to be high at end of external space access cycle.
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Section 6 Bus Controller (BSC) External space read T1 CPU cycle External bus released state T2 φ SDRAMφ High-Z Address bus High-Z Data bus High-Z Row address Precharge-sel High-Z RAS High-Z CAS High-Z WE High-Z CKE High-Z DQMU, DQML BREQ BACK BREQO NOP PALL [1] [2] NOP [3] NOP [4] [5] [8] [6] [7] [9] [1] Low level of BREQ signal is sampled at rise of f. [2] PLL command is issued. [3] Bus control signal returns to be high at end of external space access cycle.
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Section 6 Bus Controller (BSC) 6.12 Bus Arbitration This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration). There are four bus masters—the CPU, DTC, DMAC, and EXDMAC—that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
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Section 6 Bus Controller (BSC) CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, DMAC, or EXDMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations.
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Section 6 Bus Controller (BSC) temporary release of the bus in the event of an external access request from an internal bus master. For details see section 8, EXDMA Controller. External Bus Release: When the BREQ pin goes low and an external bus release request is issued while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter. External bus release can be performed on completion of an external bus cycle. 6.
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Section 6 Bus Controller (BSC) 6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the BREQOE bit to 1 in BCR beforehand enables the BREQO signal to be output when a CBR refresh/auto refresh request is issued. Note: In the H8S/2678 Group, the auto refresh control is not supported. 6.14.
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Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.
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Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1.
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Section 7 DMA Controller (DMAC) 7.2 Input/Output Pins Table 7.1 shows the DMAC pin configuration. Table 7.
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Section 7 DMA Controller (DMAC) • DMA control register_1A (DMACR_1A) • DMA control register_1B (DMACR_1B) • DMA band control register H (DMABCRH) • DMA band control register L (DMABCRL) • DMA write enable register (DMAWER) • DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode). The transfer mode can be selected by means of the FAE1 and FAE0 bits in DMABCRH.
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Section 7 DMA Controller (DMAC) 7.3.1 Memory Address Registers (MARA and MARB) MAR is a 32-bit readable/writable register that specifies the source address (transfer source address) or destination address (transfer destination address). MAR consists of two 16-bit registers MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified.
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Section 7 DMA Controller (DMAC) 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0 (channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B). ETCR is not initialized by a reset or in standby mode.
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Section 7 DMA Controller (DMAC) 7.3.4 DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B). In short address mode, channels A and B operate independently, and in full address mode, channels A and B operate together.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 RPE 0 R/W Repeat Enable Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description • Channel A 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Setting prohibited 0011: Setting prohibited 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description • Channel B 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Activated by DREQ pin rising edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission
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Section 7 DMA Controller (DMAC) Full Address Mode: • DMACR_0A and DMACR_1A Bit Bit Name Initial Value R/W 15 DTSZ 0 R/W Description Data Transfer Size Selects the size of data to be transferred at one time.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 10 to 8  All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. Legend: x: Don't care • DMACR_0B and DMACR_1B Bit Bit Name Initial Value R/W Description 7  0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description • Normal Mode 0000: Setting prohibited 0001: Setting prohibited 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 010x: Setting prohibited 0110: Auto-request (cycle steal) 0111: Auto-request (burst) 1xxx: Setting prohibited • Block Transfer Mode 0000: Setting prohibited 0001: Activated by A/D converter conversion
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Legend: x: Don't care 7.3.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 13 SAE1 0 R/W Single Address Enable 1 Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode 12 SAE0 0 R/W Single Address Enable 0 Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode.
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Section 7 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 6 5 4 DTE1B DTE1A DTE0B DTE0A 0 0 0 0 R/W R/W R/W R/W Data Transfer Enable 1B Data Transfer Enable 1A Data Transfer Enable 0B Data Transfer Enable 0A If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
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Section 7 DMA Controller (DMAC) Full Address Mode: • DMABCRH Bit Bit Name Initial Value R/W 15 FAE1 0 R/W Description Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as channel 1. 0: Short address mode 1: Full address mode 14 FAE0 0 R/W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 11 DTA1 0 R/W Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1. It the DTA1 bit is set to 1 when DTE1 = 1, the internal interrupt source is cleared automatically by DMA transfer.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 9 DTA0 0 R/W Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE0 = 1 and DTA0 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC.
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Section 7 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTME1 0 R/W Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel 1. If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 6 DTE1 0 R/W Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 DTME0 0 R/W Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel 0. If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 4 DTE0 0 R/W Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
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Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE1 bit is cleared to 0 when DTIE1A= 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
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Section 7 DMA Controller (DMAC) 7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned.
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Section 7 DMA Controller (DMAC) chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of other channels. First transfer area MAR_0A IOAR_0A ETCR_0A MAR_0B IOAR_0B ETCR_0B MAR_1A DTC IOAR_1A ETCR_1A MAR_1B IOAR_1B ETCR_1B Second transfer area using chain transfer DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B DMABCR Figure 7.
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Section 7 DMA Controller (DMAC) 7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The TEND pin is available only for channel B in short address mode. Except for the block transfer mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents reaches 0 regardless of the activation source.
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Section 7 DMA Controller (DMAC) 7.4 Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.
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Section 7 DMA Controller (DMAC) 7.4.1 Activation by Internal Interrupt Request An interrupt request selected as a DMAC activation source can also simultaneously generate an interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt request, the DMAC accepts the interrupt request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant.
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Section 7 DMA Controller (DMAC) 7.4.3 Activation by Auto-Request Auto-request is activated by register setting only, and transfer continues to the end. With autorequest activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles are usually repeated alternately.
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Section 7 DMA Controller (DMAC) Transfer Mode Full address mode Normal mode Transfer Source Remarks Auto-request • Max.
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Section 7 DMA Controller (DMAC) 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.5 summarizes register functions in sequential mode. Table 7.
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Section 7 DMA Controller (DMAC) Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where: L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends.
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Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Sequential mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACR.
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Section 7 DMA Controller (DMAC) by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in idle mode. Table 7.
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Section 7 DMA Controller (DMAC) Figure 7.6 shows an example of the setting procedure for idle mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Idle mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR.
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Section 7 DMA Controller (DMAC) 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRL. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues.
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Section 7 DMA Controller (DMAC) In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below.
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Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Figure 7.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode.
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Section 7 DMA Controller (DMAC) 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCRH to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.
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Section 7 DMA Controller (DMAC) Address T DACK Transfer 1-byte or -word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where: L = Value set in MAR N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified) Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Rev. 3.
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Section 7 DMA Controller (DMAC) Single address mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR.
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Section 7 DMA Controller (DMAC) 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.
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Section 7 DMA Controller (DMAC) Transfer Address TA Address BB Address BA Legend: Address Address Address Address Where: TA TB BA BB LA LB N Address TB = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7.11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests.
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Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Normal mode setting Set DMABCRH [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA.
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Section 7 DMA Controller (DMAC) 7.5.7 Block Transfer Mode In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB.
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Section 7 DMA Controller (DMAC) Address TB Address TA 1st block 2nd block Block area Transfer Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend: Address Address Address Address Where: TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (M·N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.
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Section 7 DMA Controller (DMAC) Address TA Address TB Block area Transfer 1st block Consecutive transfer of M bytes or words is performed in response to one request Address BA 2nd block Nth block Address BB Legend: Address Address Address Address Where: TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (M·N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.
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Section 7 DMA Controller (DMAC) ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7.15 shows the operation flow in block transfer mode.
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Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
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Section 7 DMA Controller (DMAC) 7.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations.
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Section 7 DMA Controller (DMAC) 7.5.9 DMA Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7.18 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
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Section 7 DMA Controller (DMAC) Full Address Mode (Cycle Steal Mode): Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
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Section 7 DMA Controller (DMAC) Full Address Mode (Burst Mode): Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Last transfer cycle Bus release Bus release Burst transfer Figure 7.
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Section 7 DMA Controller (DMAC) Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
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Section 7 DMA Controller (DMAC) DMA read Bus release DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination φ DREQ Address bus DMA control Channel Transfer source Transfer destination Idle Read Write Idle Read Request clear period Request [1] [2] Idle Request clear period Request Minimum of 2 cycles Write Minimum of 2 cycles [3] [4] [5] Acceptance resumes [6] [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level
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Section 7 DMA Controller (DMAC) 1 block transfer 1 block transfer DMA read Bus release DMA write DMA Bus dead release DMA read DMA write DMA dead Bus release φ DREQ Address bus DMA control Channel Transfer source Read Idle Request Transfer destination Dead Write Request clear period Idle [2] Read Write Transfer destination Dead Idle Request clear period Request Minimum of 2 cycles [1] Transfer source Minimum of 2 cycles [3] [4] [5] [6] [7] Acceptance resumes Acceptance re
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Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing (Normal Mode): Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level.
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Section 7 DMA Controller (DMAC) 1 block transfer DMA read Bus release 1 block transfer DMA write DMA Bus dead release DMA read DMA write DMA dead Bus release φ DREQ Address bus DMA control Channel Transfer source Idle Read Dead Write Request clear period Request Idle [2] Read Write Transfer destination Dead Idle Request clear period Request Minimum of 2 cycles [1] Transfer source Transfer destination Minimum of 2 cycles [3] [4] [5] [6] Acceptance resumes [7] Acceptance re
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Section 7 DMA Controller (DMAC) 7.5.10 DMA Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 7.26 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA DMA read dead φ Address bus RD DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.
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Section 7 DMA Controller (DMAC) Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA dead φ Address bus RD DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
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Section 7 DMA Controller (DMAC) Single Address Mode (Write): Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA DMA write dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.28 Example of Single Address Mode Transfer (Byte Write) Rev. 3.
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Section 7 DMA Controller (DMAC) Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
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Section 7 DMA Controller (DMAC) Bus release DMA single Bus release DMA single Bus release φ DREQ Transfer source/ destination Address bus Transfer source/ destination DACK DMA control Channel Single Idle Request Single Idle Request clear period [1] [2] Request clear period Request Minimum of 2 cycles Idle Minimum of 2 cycles [3] [4] [5] Acceptance resumes [6] [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, a
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Section 7 DMA Controller (DMAC) Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low level.
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Section 7 DMA Controller (DMAC) request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.11 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved.
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Section 7 DMA Controller (DMAC) DMA read DMA single CPU read DMA single CPU read φ Internal address Internal read signal External address RD DACK Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer. 7.5.
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Section 7 DMA Controller (DMAC) channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
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Section 7 DMA Controller (DMAC) 7.5.14 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
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Section 7 DMA Controller (DMAC) [1] Forced termination of DMAC Clear DTE bit to 0 Clear the DTE bit in DMABCRL to 0. To prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. [1] Forced termination Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation 7.5.16 Clearing Full Address Mode Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address mode.
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Section 7 DMA Controller (DMAC) 7.6 Interrupt Sources The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12 shows the interrupt sources and their priority order. Table 7.
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Section 7 DMA Controller (DMAC) 7.7 Usage Notes 7.7.1 DMAC Register Access during Operation Except for forced termination of the DMAC, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
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Section 7 DMA Controller (DMAC) • If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.40. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA read DMA write φ DMA internal address DMA control Idle DMA register operation Transfer source Transfer destination Read Write [1] Idle [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7.
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Section 7 DMA Controller (DMAC) • Write data buffer function and DMAC register setting If the setting of a register that controls external accesses is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. Registers that control external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access.
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Section 7 DMA Controller (DMAC) DMA read DMA write φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. Figure 7.41 Example in Which Low Level Is Not Output at TEND Pin 7.7.5 Activation by Falling Edge on DREQ Pin DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
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Section 7 DMA Controller (DMAC) 7.7.6 Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before write to DMABCRL to enable transfer.
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Section 8 EXDMA Controller Section 8 EXDMA Controller This LSI has a built-in four-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (DMA transfer notification) facility. 8.
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Section 8 EXDMA Controller Bus controller Data buffer Control logic EDRAK Processor ETEND EDACK Interrupt request signals to CPU for individual channels Address buffer EDSAR EDDAR EDMDR EDACR EDTCR Internal data bus Legend: EDSAR: EDDAR: EDTCR: EDMDR: EDACR: EXDMA source address register EXDMA destination address register EXDMA transfer count register EXDMA mode control register EXDMA address control register Figure 8.1 Block Diagram of EXDMAC Rev. 3.
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Section 8 EXDMA Controller 8.2 Input/Output Pins Table 8.1 shows the EXDMAC pin configuration. Table 8.
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Section 8 EXDMA Controller 8.3 Register Descriptions The EXDMAC has the following registers.
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Section 8 EXDMA Controller 8.3.2 EXDMA Destination Address Register (EDDAR) EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An address update function is provided that updates the register contents to the next transfer destination address each time transfer processing is performed. In single address mode, the EDDAR value is ignored when a device with DACK is specified as the transfer destination.
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Section 8 EXDMA Controller Block Transfer Mode: Bit Bit Name Initial Value R/W Description 31 to 24 — All 0 — Reserved These bits are always read as 0 and cannot be modified. 23 to 16 Undefined 15 to 0 Undefined R/W Block Size These bits specify the block size (number of bytes or number of words) for block transfer. Setting H'01 specifies one as the block, while setting H'00 specifies the maximum block size, that is 256. The register value always indicates the specified block size.
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Section 8 EXDMA Controller 8.3.4 EXDMA Mode Control Register (EDMDR) EDMDR controls EXDMAC operations. Bit Bit Name Initial Value R/W Description 15 EDA 0 R/(W) EXDMA Active Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress. When auto request mode is specified (by bits MDS1 and MDS0), transfer processing begins when this bit is set to 1.
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Section 8 EXDMA Controller Bit Bit Name Initial Value R/W Description 14 BEF 0 R/(W)* Block Transfer Error Flag Flag that indicates the occurrence of an error during block transfer. If an NMI interrupt is generated during block transfer, the EXDMAC immediately terminates the EXDMA operation and sets this bit to 1. The address registers indicate the next transfer addresses, but the data for which transfer has been performed within the block size is lost.
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Section 8 EXDMA Controller Bit Bit Name Initial Value R/W Description 10 AMS 0 R/W Address Mode Select Selects single address mode or dual address mode. When single address mode is selected, the EDACK pin is valid. 0: Dual address mode 1: Single address mode 9 8 MDS1 MDS0 0 0 R/W R/W Mode Select 1 and 0 These bits specify the activation source, bus mode, and transfer mode.
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Section 8 EXDMA Controller Bit Bit Name Initial Value R/W Description 6 IRF 0 R/(W)* Interrupt Request Flag Flag indicating that an interrupt request has occurred and transfer has ended.
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Section 8 EXDMA Controller Bit Bit Name Initial Value R/W Description 3 DTSIZE 0 R/W Data Transmit Size Specifies the size of data to be transferred. 0: Byte-size 1: Word-size 2 BGUP 0 R/W Bus Give-Up When this bit is set to 1, the bus can be transferred to an internal bus mastership in burst mode or block transfer mode. This setting is ignored in normal mode and cycle steal mode.
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Section 8 EXDMA Controller 8.3.5 EXDMA Address Control Register (EDACR) EDACR specifies address register incrementing/decrementing and use of the repeat area function. Bit Bit Name Initial Value R/W Description 15 14 SAT1 SAT0 0 0 R/W R/W Source Address Update Mode These bits specify incrementing/decrementing of the transfer source address (EDSAR). When an external device with DACK is designated as the transfer source in single address mode, the specification by these bits is ignored.
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Section 8 EXDMA Controller Bit Bit Name Initial Value R/W Description 12 11 10 9 8 SARA4 SARA3 SARA2 SARA1 SARA0 0 0 0 0 0 R/W R/W R/W R/W R/W Source Address Repeat Area These bits specify the source address (EDSAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a power-oftwo number of bytes.
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Section 8 EXDMA Controller Bit Bit Name Initial Value R/W Description 7 6 DAT1 DAT0 0 0 R/W R/W Destination Address Update Mode These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When an external device with DACK is designated as the transfer destination in single address mode, the specification by these bits is ignored.
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Section 8 EXDMA Controller Bit Bit Name Initial Value R/W Description 4 3 2 1 0 DARA4 DARA3 DARA2 DARA1 DARA0 0 0 0 0 0 R/W R/W R/W R/W R/W Destination Address Repeat Area These bits specify the destination address (EDDAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a power-of-two number of bytes.
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Section 8 EXDMA Controller 8.4 Operation 8.4.1 Transfer Modes The transfer modes of the EXDMAC are summarized in table 8.2. Table 8.
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Section 8 EXDMA Controller In block transfer mode, a transfer of the specified block size is executed in response to one transfer request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be performed at the same high speed as in block transfer mode. When the “no specification” setting (EDTCR = H'000000) is made for the number of transfers, the transfer counter is halted and there is no limit on the number of transfers, allowing transfer to be performed endlessly.
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Section 8 EXDMA Controller EXDMA read cycle EXDMA write cycle φ Address bus EDSAR EDDAR RD WR ETEND Figure 8.2 Example of Timing in Dual Address Mode Single Address Mode: In single address mode, the EDACK signal is used instead of the source or destination address register to transfer data directly between an external device and external memory.
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Section 8 EXDMA Controller External address bus External data bus Microcomputer External memory EXDMAC External device with DACK EDACK EDREQ Data flow Figure 8.3 Data Flow in Single Address Mode Rev. 3.
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Section 8 EXDMA Controller Transfer from external memory to external device with DACK EXDMA cycle φ Address bus EDSAR RD Address to external memory space RD signal to external memory space WR EDACK Data output from external memory Data bus ETEND Transfer from external device with DACK to external memory EXDMA cycle φ Address bus EDDAR Address to external memory space RD WR WR signal to external memory space EDACK Data output from external device with DACK Data bus ETEND Figure 8.
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Section 8 EXDMA Controller 8.4.3 DMA Transfer Requests Auto Request Mode: In auto request mode, transfer request signals are automatically generated within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to 1 in EDMDR.
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Section 8 EXDMA Controller takes back the bus, performs another transfer-unit transfer, and then releases the bus again. This procedure is repeated until the transfer end condition is satisfied. If a transfer request occurs in another channel during DMA transfer, the bus is temporarily released, then transfer is performed on the channel for which the transfer request was issued. If there is no external space bus request from another bus master, a one-cycle bus release interval is inserted.
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Section 8 EXDMA Controller When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another bus mastership during burst transfer. If there is no bus request, burst transfer is executed even if the BGUP bit is set to 1. Figure 8.6 shows examples of the timing in burst mode.
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Section 8 EXDMA Controller Bus cycle EXDMA transfer cycle Last EXDMA transfer cycle Read Read Write Write ETEND Transfer conditions: Dual address mode, auto request mode EDREQ EDRAK Bus cycle EXDMA EXDMA EDACK Transfer conditions: Single address mode, external request mode Figure 8.7 Examples of Timing in Normal Transfer Mode Block Transfer Mode: In block transfer mode, the number of bytes or words specified by the block size is transferred in response to one transfer request.
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Section 8 EXDMA Controller Caution is required when setting the repeat area overflow interrupt of the repeat area function in block transfer mode. See section 8.4.6, Repeat Area Function, for details. Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA Transfer, for details. Figure 8.8 shows an example of DMA transfer timing in block transfer mode.
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Section 8 EXDMA Controller The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat area can be specified independently. When the address register value is the last address in the repeat area and repeat area overflow occurs, DMA transfer can be temporarily halted and an interrupt request sent to the CPU.
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Section 8 EXDMA Controller mode, the block size must be a power of two, or alternatively, the address register value must be set so that the end of a block coincides with the end of the repeat area range. If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat interrupt request is held pending until the end of the block, and transfer overrun will occur. Figure 8.10 shows an example in which block transfer mode is used together with the repeat area function.
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Section 8 EXDMA Controller accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented when SAT1 = 1 and SAT0 = 1. The size of the increment or decrement is determined by the size of the data transferred.
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Section 8 EXDMA Controller EXDMA Transfer Count Register (EDTCR): When a DMA transfer is performed, the value in EDTCR is decremented by 1. However, when the EDTCR value is 0, transfers are not counted and the EDTCR value does not change. EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to specify the block size, and their value does not change.
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Section 8 EXDMA Controller EDTCR in normal transfer mode Before update 23 EDTCR Fixed 23 0 0 23 EDTCR After update 0 0 0 –1 23 1 to H'FFFFFF 0 0 to H'FFFFFE EDTCR in block transfer mode EDTCR Before update 23 16 15 Block 0 size EDTCR 23 16 15 Block 1 to H'FFFF size 0 0 Fixed –1 After update 23 16 15 Block 0 size 23 16 15 Block 0 to H'FFFE size 0 0 Figure 8.
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Section 8 EXDMA Controller In burst mode, transfer is halted for up to three DMA transfers following the bus cycle in which 0 is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until the end of the last DMA cycle. Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that the EDA bit has been cleared to 0. Figure 8.
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Section 8 EXDMA Controller IRF Bit in EDMDR: The IRF bit in EDMDR is set to 1 when an interrupt request source occurs. If the EDIE bit in EDMDR is 1 at this time, an interrupt is requested. The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer ends following the end of the DMA transfer bus cycle in which the source generating the interrupt occurred.
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Section 8 EXDMA Controller Channel 0 transfer Channel 1 transfer Channel 2 transfer φ Channel 0 Address bus EXDMA control Idle Channel 0 Bus release Channel 1 Channel 0 Request cleared Channel 1 Request Selected held Channel 2 Not Request Request selected held held Channel 1 Bus release Channel 2 Channel 2 Request cleared Selected Request cleared Figure 8.
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Section 8 EXDMA Controller Conditions (1) Channel 0: Auto request, cycle steal mode Channel 1: External request, cycle steal mode, low level activation Bus Channel 0 * Channel 0 * Channel 0 * Channel 1 * Channel 1 * Channel 0 EDA bit Channel 1/ EDREQ1 pin Conditions (2) Channel 1: External request, cycle steal mode, low level activation Channel 2: Auto request, cycle steal mode Bus Channel 2 * Channel 2 * Channel 1 * Channel 2 * Channel 1 * Channel 0 * Channel 0 * Channel 2 Cha
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Section 8 EXDMA Controller 8.4.9 EXDMAC Bus Cycles (Dual Address Mode) Normal Transfer Mode (Cycle Steal Mode): Figure 8.15 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. After one byte or word has been transferred, the bus is released. While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated.
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Section 8 EXDMA Controller Normal Transfer Mode (Burst Mode): Figure 8.16 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. In burst mode, one-byte or one-word transfers are executed continuously until transfer ends. Once burst transfer starts, requests from other channels, even of higher priority, are held pending until transfer ends.
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Section 8 EXDMA Controller Block Transfer Mode (Cycle Steal Mode): Figure 8.17 shows an example of transfer when ETEND output is enabled, and word-size, block transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. One block is transferred in response to one transfer request, and after the transfer, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
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Section 8 EXDMA Controller EDREQ Pin Falling Edge Activation Timing: Figure 8.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge.
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Section 8 EXDMA Controller One block transfer One block transfer DMA read DMA write Transfer source Transfer destination Bus release Bus release DMA read DMA write Bus release φ EDREQ Address bus DMA control Idle Read Channel Idle Read Write Request clearance period Request Minimum 3 cycles [1] Write Transfer source [2] [3] Idle Request clearance period Request Minimum 3 cycles [4] [5] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Transfer destination [6] [7] Acceptance
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Section 8 EXDMA Controller EDREQ Pin Low Level Activation Timing: Figure 8.20 shows an example of normal mode transfer activated by the EDREQ pin low level.
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Section 8 EXDMA Controller One block transfer Bus release One block transfer DMA read DMA write Transfer source Transfer destination Bus release DMA read DMA write Bus release φ EDREQ Address bus DMA control Idle Read Channel Write Transfer source Idle Read Write Request clearance period Request [2] [3] Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Idle Request clearance period Request Minimum 3 cycles [1] Transfer destination [5] [6] [7] Acceptance res
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Section 8 EXDMA Controller 8.4.10 EXDMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 8.22 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2state access space to an external device. DMA read DMA read DMA read DMA read φ Address bus RD EDACK ETEND Bus release Bus release Bus release Bus release Last Bus release transfer cycle Figure 8.
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Section 8 EXDMA Controller Single Address Mode (Write): Figure 8.24 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA write φ Address bus HWR LWR EDACK ETEND Bus release Bus release Bus release Bus release Last Bus release transfer cycle Figure 8.24 Example of Single Address Mode (Byte Write) Transfer Figure 8.
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Section 8 EXDMA Controller After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. EDREQ Pin Falling Edge Activation Timing: Figure 8.26 shows an example of single address mode transfer activated by the EDREQ pin falling edge.
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Section 8 EXDMA Controller EDREQ Pin Low Level Activation Timing: Figure 8.27 shows an example of single address mode transfer activated by the EDREQ pin low level.
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Section 8 EXDMA Controller 8.4.11 Examples of Operation Timing in Each Mode Auto Request/Cycle Steal Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a onecycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the next transfer.
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Section 8 EXDMA Controller φ pin 1 bus cycle Bus cycle CPU cycle CPU operation External space EXDMA single transfer cycle CPU cycle External space Last transfer cycle EXDMA single transfer cycle CPU cycle EXDMA single transfer cycle External space CPU cycle External space EDACK ETEND Figure 8.
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Section 8 EXDMA Controller Auto Request/Burst Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is satisfied. If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another bus master. Transfer requests for other channels are held pending until the end of transfer on the current channel. Figures 8.31 to 8.
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Section 8 EXDMA Controller φ pin Last transfer cycle 1 bus cycle Bus cycle CPU operation EXDMA EXDMA EXDMA EXDMA EXDMA CPU cycle CPU cycle single cycle single cycle CPU cycle single cycle single cycle CPU cycle single cycle CPU cycle External space External space External space External space External space EDACK ETEND Figure 8.
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Section 8 EXDMA Controller External Request/Cycle Steal Mode/Normal Transfer Mode: In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted. The next transfer request is accepted after the end of a one-transfer-unit EXDMA cycle. For external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA cycle.
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Section 8 EXDMA Controller φ pin EDREQ EDRAK 2 bus cycles Bus cycle CPU operation CPU cycle CPU cycle CPU cycle External space External space External space EXDMA single transfer cycle CPU cycle CPU cycle External space External space Last transfer cycle EXDMA single transfer cycle CPU cycle External space EDACK ETEND Figure 8.
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Section 8 EXDMA Controller φ pin Original channel EDREQ Original channel EDRAK 1 cycle 3 cycles Bus cycle EXDMA transfer cycle Bus release EXDMA read 1 cycle Other channel transfer cycle EXDMA write Bus release EXDMA read EXDMA write Bus release Other channel EDREQ Other channel EDRAK Figure 8.
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EDA bit ETEND Bus cycle EDRAK EDREQ φ pin 1 Bus release EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write Last transfer in block Repeated 1-block-size transfer period Bus release 3 cycles EXDMA read EXDMA write Repeated EXDMA read 0 EXDMA write Bus release Last transfer cycle Last block Section 8 EXDMA Controller Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0) Rev. 3.
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Rev. 3.00 Mar 17, 2006 page 388 of 926 REJ09B0283-0300 ETEND EDACK Bus cycle EDRAK EDREQ φ pin Bus release EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Last transfer in block Repeated 1-block-size transfer period Bus release 3 cycles EXDMA single transfer cycle Repeated EXDMA single transfer cycle Bus release Last transfer cycle Last block Section 8 EXDMA Controller Figure 8.
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ETEND EDACK CPU operation Bus cycle EDRAK EDREQ φ pin External space CPU cycle External space CPU cycle External space CPU cycle External space EXDMA single transfer cycle Repeated EXDMA single transfer cycle Last transfer in block 1-block-size transfer period CPU cycle External space CPU cycle 2 bus cycles External space EXDMA single transfer cycle Repeated EXDMA single transfer cycle Last transfer in block 1-block-size transfer period CPU cycle Section 8 EXDMA Controller Figu
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Rev. 3.
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External space External space CPU operation ETEND EDACK CPU cycle CPU cycle Bus cycle EDRAK EDREQ φ pin External space CPU cycle External space EXDMA EXDMA transfer cycle transfer cycle CPU cycle 1 bus cycle External space EXDMA EXDMA transfer cycle transfer cycle CPU cycle 1 bus cycle External space Repeated EXDMA transfer cycle 1-block-size transfer period CPU cycle 1 bus cycle External space EXDMA EXDMA transfer cycle transfer cycle Last transfer in block CPU cycle External
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Rev. 3.00 Mar 17, 2006 page 392 of 926 REJ09B0283-0300 Other channel EDRAK Other channel EDREQ ETEND Bus cycle EDRAK EDREQ φ pin Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Last transfer in block 1-block-size transfer period Bus release Other channel EXDMA cycle Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Last transfer in block 1-block-size transfer period Section 8 EXDMA Controller Figure 8.
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Section 8 EXDMA Controller 8.4.12 Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has ended. Transfer End by 1 → 0 Transition of EDTCR: When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0.
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Section 8 EXDMA Controller In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the block transfer was not carried out normally. When transfer is aborted, register values are retained, and as the address registers indicate the next transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR.
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Section 8 EXDMA Controller 8.5 Interrupt Sources EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area overflow interrupts. Table 8.4 shows the interrupt sources and their priority order. Table 8.
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Section 8 EXDMA Controller Interrupt source settings are made individually with the interrupt enable bits in the registers for the relevant channels. The transfer counter’s transfer end interrupt is enabled or disabled by means of the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of the SARIE bit in EDACR, and the destination address register repeat area overflow interrupt by means of the DARIE bit in EDACR.
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Section 8 EXDMA Controller Transfer end interrupt exception handling routine Transfer restart after end of interrupt handling routine Transfer continuation processing Change register settings [1] Clear IRF bit to 0 [4] Write 1 to EDA bit [2] End of interrupt handling routine [5] End of interrupt handling routine (RTE instruction execution) [3] Change register settings [6] Write 1 to EDA bit [7] End of transfer restart processing End of transfer restart processing [1] Write set values to t
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Section 8 EXDMA Controller 8.6 Usage Notes 8.6.1 EXDMAC Register Access during Operation Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel. 8.6.2 Module Stop State When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC enters the module stop state.
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Section 8 EXDMA Controller 8.6.4 Activation Source Acceptance At the start of activation source acceptance, low level sensing is used for both falling edge sensing and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transferenabled state.
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Section 8 EXDMA Controller Rev. 3.
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Section 9 Data Transfer Controller (DTC) Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC. The DTC’s register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.
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Section 9 Data Transfer Controller (DTC) Internal address bus Register information MRA MRB CRA CRB DAR SAR Control logic CPU interrupt request Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERG DTVECR On-chip RAM DTC DTC activation request DTVECR Interrupt request DTCERA to DTCERG Interrupt controller Internal data bus : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to G : DTC vector r
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Section 9 Data Transfer Controller (DTC) 9.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 6 SM1 SM0 Undefined Undefined — — Source Address Mode 1 and 0 These bits specify an SAR operation after a data transfer.
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Section 9 Data Transfer Controller (DTC) Bit Bit Name Initial Value R/W Description 0 Sz Undefined — DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer Legend: X: Don’t care 9.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 CHNE Undefined — DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 9.5.
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Section 9 Data Transfer Controller (DTC) 9.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 9.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 9.2.
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Section 9 Data Transfer Controller (DTC) Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source.
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Section 9 Data Transfer Controller (DTC) 9.3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0.
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Section 9 Data Transfer Controller (DTC) 9.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF). Register information should be located at the address that is multiple of four within the range. Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information.
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Section 9 Data Transfer Controller (DTC) Table 9.
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Section 9 Data Transfer Controller (DTC) Origin of Activation Source TPU_4 TPU_5 TMR_0 TMR_1 DMAC SCI_0 SCI_1 SCI_2 Note: 9.
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Section 9 Data Transfer Controller (DTC) The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Figure 9.4 shows a flowchart of DTC operation, and table 9.2 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted).
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Section 9 Data Transfer Controller (DTC) Table 9.
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Section 9 Data Transfer Controller (DTC) SAR DAR Transfer Figure 9.5 Memory Mapping in Normal Mode 9.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 9.4 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
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Section 9 Data Transfer Controller (DTC) SAR or DAR DAR or SAR Repeat area Transfer Figure 9.6 Memory Mapping in Repeat Mode 9.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 9.5 lists the register function in block transfer mode. The block size is 1 to 256.
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Section 9 Data Transfer Controller (DTC) First block SAR or DAR Block area Transfer DAR or SAR Nth block Figure 9.7 Memory Mapping in Block Transfer Mode 9.5.4 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.8 shows the operation of chain transfer.
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Section 9 Data Transfer Controller (DTC) Source Destination Register information CHNE=1 DTC vector address Register information start address Register information CHNE=0 Source Destination Figure 9.8 Operation of Chain Transfer 9.5.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1.
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Section 9 Data Transfer Controller (DTC) 9.5.6 Operation Timing φ DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 9.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 9.
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Section 9 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer information write Transfer information read Transfer information write Figure 9.11 DTC Operation Timing (Example of Chain Transfer) 9.5.7 Number of DTC Execution States Table 9.6 lists execution status for a single DTC data transfer, and table 9.7 shows the number of states required for each execution status.
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Section 9 Data Transfer Controller (DTC) Table 9.
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Section 9 Data Transfer Controller (DTC) 9.6 Procedures for Using DTC 9.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1.
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Section 9 Data Transfer Controller (DTC) 9.7 Examples of Use of the DTC 9.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
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Section 9 Data Transfer Controller (DTC) 9.7.2 Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half.
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Section 9 Data Transfer Controller (DTC) 9.7.3 Chain Transfer when Counter = 0 By executing a second data transfer, and performing re-setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 9.12 shows the chain transfer when the counter value is 0. 1.
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Section 9 Data Transfer Controller (DTC) Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 9.12 Chain Transfer when Counter = 0 Rev. 3.
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Section 9 Data Transfer Controller (DTC) 9.7.4 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).
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Section 9 Data Transfer Controller (DTC) 9.8 Usage Notes 9.8.1 Module Stop Mode Setting DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting module stop mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 22, Power-Down Modes. 9.8.2 On-Chip RAM The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM.
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Section 10 I/O Ports Section 10 I/O Ports Table 10.1 summarizes the port functions. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR or DDR register.
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Section 10 I/O Ports Table 10.
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Section 10 I/O Ports Port Description Port General I/O port 4 also functioning as A/D converter analog inputs and D/A converter analog outputs Modes 1 Modes 2 Mode 4 and 5 and 6 Modes 3*1, 7 EXPE = 1 EXPE = 0 Input/ Output Type P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Port General I/O port 5 also functioning as interrupt inputs, A/D converter analog inputs, and D/A converter analog outputs General I/O port also functioning as interrupt inputs, A/D converter analog inp
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Section 10 I/O Ports Port Description Port General I/O port 8 also functioning as EXDMAC I/Os and interrupt inputs Port General I/O port A also functioning as address outputs Port General I/O port B also functioning as address outputs Port General I/O port C also functioning as address outputs Modes 1 Modes 2 Mode 4 and 5 and 6 Modes 3*1, 7 EXPE = 1 EXPE = 0 P85/EDACK3/IRQ5 P85/EDACK3/IRQ5 P85/IRQ5 P84/EDACK2/IRQ4 P84/EDACK2/IRQ4 P84/IRQ4 P83/ETEND3/IRQ3 P83/ETEND3/IRQ3 P83/IRQ3 P82/ETEND2/I
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Section 10 I/O Ports Port Description Port General I/O port D also functioning as data I/Os Port General I/O port E also functioning as data I/Os Port General I/O port F also functioning as interrupt inputs and bus control I/Os Port General I/O port G also functioning as bus control I/Os Modes 3*1, 7 Modes 1 Modes 2 Mode 4 and 5 and 6 EXPE = 1 EXPE = 0 D15 D15 PD7 D14 D14 PD6 D13 D13 PD5 D12 D12 PD4 D11 D11 PD3 D10 D10 PD2 D9 D9 PD1 D8 D8 PD0 D7 PE7/D7 PE7/D7 PE7/D7 PE
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Section 10 I/O Ports Port Modes 3*1, 7 Modes 1 Modes 2 Mode 4 and 5 and 6 Description Port General I/O port PH3/CS7/OE/CKE*2/(IRQ7) H also functioning as interrupt inputs PH2/CS6/(IRQ6) and bus control PH1/CS5/RAS5/SDRAMφ*2 I/Os PH0/CS4/RAS4/WE*2 EXPE = 1 PH3/CS7/OE/ CKE*2/(IRQ7) EXPE = 0 PH3/(IRQ7) PH2/CS6/(IRQ6) PH2/(IRQ6) PH1/CS5/RAS5/ SDRAMφ*2 PH1/SDRAMφ*2 PH0/CS4/RAS4/ WE*2 PH0 Input/ Output Type Only PH2 and PH3 are Schmitttriggered inputs when used as the IRQ input Notes: 1.
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Section 10 I/O Ports 10.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. PORT1 cannot be modified.
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Section 10 I/O Ports 10.1.4 Pin Functions Port 1 pins also function as PPG outputs, TPU I/Os, and EXDMAC outputs. The correspondence between the register specification and the pin functions is shown below.
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Section 10 I/O Ports TPU channel 2 settings (2) MD3 to MD0 IOB3 to IOB0 (1) (2) B'0000, B'01xx (2) (1) B'0010 B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx (2) B'0011 B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output — x: Don’t care • P16/PO14/TIOCA2/EDRAK2 The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR2
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Section 10 I/O Ports Modes 3* (EXPE = 0), 7 (EXPE = 0) 3 EDRAKE TPU channel 2 settings — (1) in table below (2) in table below P16DDR — 0 1 1 NDER14 — — 0 1 TIOCA2 output P16 input P16 output Pin function TIOCA2 input* Note: PO14 output 1 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
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Section 10 I/O Ports • P15/PO13/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.
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Section 10 I/O Ports • P14/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR. TPU channel 1 settings (1) in table below (2) in table below P14DDR — 0 1 1 NDER12 — — 0 1 TIOCA1 output P14 input Pin function P14 output PO12 output TIOCA1 input* 1 Note: 1.
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Section 10 I/O Ports • P13/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR.
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Section 10 I/O Ports • P12/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR.
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Section 10 I/O Ports • P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0 and bits IOB3 to IOB0 in TIOR0H), bit NDER9 in NDERH, and bit P11DDR. TPU channel 0 settings (1) in table below (2) in table below P11DDR — 0 1 1 NDER9 — — 0 1 TIOCB0 output P11 input P11 output PO9 output Pin function TIOCB0 input* Note: * TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
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Section 10 I/O Ports • P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit NDER8 in NDERH, and bit P10DDR. TPU channel 0 settings (1) in table below (2) in table below P10DDR — 0 1 1 NDER8 — — 0 1 TIOCA0 output P10 input Pin function P10 output PO8 output TIOCA0 input* Note: 1 1.
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Section 10 I/O Ports 10.2 Port 2 Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers. • Port 2 data direction register (P2DDR) • Port 2 data register (P2DR) • Port 2 register (PORT2) 10.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read.
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Section 10 I/O Ports 10.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Bit Name Initial Value R/W Description 7 P27DR 0 R/W 6 P26DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W 10.2.3 Port 2 Register (PORT2) PORT2 shows the pin states. PORT2 cannot be modified.
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Section 10 I/O Ports 10.2.4 Pin Functions Port 2 pins also function as PPG outputs, TPU I/Os, interrupt inputs, and EXDMAC outputs. The correspondence between the register specification and the pin functions is shown below.
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Section 10 I/O Ports TPU channel 5 settings (2) MD3 to MD0 IOB3 to IOB0 (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output — x: Don’t care • P26/PO6/TIOCA5/IRQ14/EDRAK0 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR5,
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Section 10 I/O Ports Modes 3* (EXPE = 0), 7 (EXPE = 0) 4 EDRAKE TPU channel 5 settings — (1) in table below (2) in table below P26DDR — 0 1 1 NDER6 — — 0 1 TIOCA5 output P26 input P26 output Pin function PO6 output TIOCA5 input* 2 IRQ14 interrupt input* 1 Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. 2. IRQ14 input when ITS14 = 1.
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Section 10 I/O Ports • P25/PO5/TIOCB4/IRQ13 The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR4, bits IOB3 to IOB0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4), bit NDER5 in NDERL, bit P25DDR, and bit ITS13 in ITSR.
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Section 10 I/O Ports • P24/PO4/TIOCA4/IRQ12 The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR4 and bits IOA3 to IOA0 in TIOR4), bit NDER4 in NDERL, bit P24DDR, and bit ITS12 in ITSR. TPU channel 4 settings (1) in table below (2) in table below P24DDR — 0 1 1 NDER4 — — 0 1 TIOCA4 output P24 input Pin function P24 output PO4 output TIOCA4 input* IRQ12 interrupt input* 1 2 Notes: 1.
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Section 10 I/O Ports • P23/PO3/TIOCD3/IRQ11 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3), bit NDER3 in NDERL, bit P23DDR, and bit ITS11 in ITSR.
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Section 10 I/O Ports • P22/PO2/TIOCC3/IRQ10 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3), bit NDER2 in NDERL, bit P22DDR, and bit ITS10 in ITSR.
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Section 10 I/O Ports • P21/PO1/TIOCB3/IRQ9 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3), bit NDER1 in NDERL, bit P21DDR, and bit ITS9 in ITSR.
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Section 10 I/O Ports • P20/PO0/TIOCA3/IRQ8 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3), bit NDER0 in NDERL, bit P20DDR, and bit ITS8 in ITSR.
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Section 10 I/O Ports 10.3 Port 3 Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers. • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 register (PORT3) • Port 3 open drain control register (P3ODR) • Port function control register 2(PFCR2) 10.3.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be read.
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Section 10 I/O Ports 10.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value R/W 7, 6 — All 0 — Description Reserved These bits are always read as 0 and cannot be modified. 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 10.3.3 Output data for a pin is stored when the pin function is specified to a general purpose I/O. Port 3 Register (PORT3) PORT3 shows the pin states.
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Section 10 I/O Ports 10.3.4 Port 3 Open Drain Control Register (P3ODR) P3ODR controls the output status for each port 3 pin. Bit Bit Name Initial Value R/W 7, 6 — All 0 — Description Reserved These bits are always read as 0 and cannot be modified. 5 P35ODR 0 R/W 4 P34ODR 0 R/W 3 P33ODR 0 R/W 2 P32ODR 0 R/W 1 P31ODR 0 R/W 0 P30ODR 0 R/W Rev. 3.
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Section 10 I/O Ports 10.3.5 Port Function Control Register 2 (PFCR2) P3ODR controls the I/O port. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 — Reserved 3 ASOE These bits are always read as 0 and cannot be modified. 1 R/W AS Output Enable Selects to enable or disable the AS output pin. 0: PF6 is designated as I/O port 1: PF6 is designated as AS output pin 2 LWROE 1 R/W LWR Output Enable Selects to enable or disable the LWR output pin.
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Section 10 I/O Ports 10.3.6 Pin Functions Port 3 pins also function as SCI I/Os and a bus control signal output. The correspondence between the register specification and the pin functions is shown below. • P35/SCK1/OE/CKE The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, bits CKE0 and CKE1 in SCR, bits RMTS2 to RMTS0 in DRAMCR, bit OES in PFCR2, and bit P35DDR.
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Section 10 I/O Ports Modes 3* (EXPE = 0), 7 (EXPE = 0) 2 OEE — OES — CKE1 0 C/A — 0 CKE0 0 P35DDR Pin function 1 — 1 — — 0 1 — — — P35 input P35 1 output* SCK1 1 output* SCK1 1 output* SCK1 input Notes: 1. NMOS open-drain output when P35ODR = 1. 2. Only in H8S/2678R Group. • P34/SCK0 The pin function is switched as shown below according to the combination of bit C/A in SMR of SCI_0, bits CKE0 and CKE1 in SCR, and bit P34DDR.
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Section 10 I/O Ports • P32/RxD0/IrRxD The pin function is switched as shown below according to the combination of bit RE in SCR of SCI_0 and bit P32DDR. RE 0 P32DDR Pin function Note: * 1 0 1 — P32 input P32 output* RxD0/IrRxD input NMOS open-drain output when P32ODR = 1. • P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_1 and bit P31DDR.
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Section 10 I/O Ports 10.4 Port 4 Port 4 is an 8-bit input-only port. Port 4 has the following register. • Port 4 register (PORT4) 10.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows port 4 pin states. PORT4 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P47 R 6 P46 Undefined* Undefined* The pin states are always read when a port 4 read is performed.
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Section 10 I/O Ports • P45/AN5 Pin function AN5 input • P44/AN4 Pin function AN4 input • P43/AN3 Pin function AN3 input • P42/AN2 Pin function AN2 input • P41/AN1 Pin function AN1 input • P40/AN0 Pin function 10.5 AN0 input Port 5 Port 5 comprises a 4-bit I/O port (P53 to P50) and a 4-bit input-only port (P57 to P54). The 4-bit input-only port does not have the data direction register and data register. The port 5 has the following registers.
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Section 10 I/O Ports 10.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 — Reserved 3 P53DDR 0 W 2 P52DDR 0 W 1 P51DDR 0 W 0 P50DDR 0 W These bits are always read as 0 and cannot be modified. 10.5.
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Section 10 I/O Ports 10.5.3 Port 5 Register (PORT5) PORT5 shows the pin states. PORT5 cannot be modified. Bit Bit Name Initial Value R/W Description P57 Undefined* R 6 P56 R When bits P57 to P54 are read, the pin states are always read from bits 7 to 4. 5 P55 Undefined* Undefined* 4 P54 R 3 P53 Undefined* Undefined* 2 P52 Undefined* R 1 P51 R 0 P50 Undefined* Undefined* 7 Note: * 10.5.
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Section 10 I/O Ports • P56/AN14/DA2/IRQ6 The pin function is switched as shown below according to bit ITS6 in ITSR. IRQ6 interrupt input pin* Pin function AN14 input DA2 output Note: * IRQ6 input when ITS6 = 0. • P55/AN13/IRQ5 The pin function is switched as shown below according to bit ITS5 in ITSR. IRQ5 interrupt input* Pin function AN13 input Note: * IRQ5 input when ITS5 = 0. • P54/AN12/IRQ4 The pin function is switched as shown below according to bit ITS4 in ITSR.
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Section 10 I/O Ports • P52/SCK2/IRQ2 The pin function is switched as shown below according to the combination of bit C/A in SMR of SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR. CKE1 0 C/A 0 CKE0 0 P52DDR Pin function Note: 1 * 1 — 1 — — — 0 1 — P52 input P52 output SCK2 output — SCK2 output IRQ2 interrupt input* SCK2 input IRQ2 input when ITS2 = 0.
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Section 10 I/O Ports 10.6 Port 6 Port 6 is a 6-bit I/O port that also has other functions. The port 6 has the following registers. For details on the port function control register 2, refer to section 10.3.5, Port Function Control Register 2 (PFCR2). • Port 6 data direction register (P6DDR) • Port 6 data register (P6DR) • Port 6 register (PORT6) • Port function control register 2 (PFCR2) 10.6.
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Section 10 I/O Ports 10.6.2 Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit Bit Name Initial Value R/W 7, 6 — All 0 — Description Reserved These bits are always read as 0 and cannot be modified. 5 P65DR 0 R/W 4 P64DR 0 R/W 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0 P60DR 0 R/W 10.6.3 An output data for a pin is stored when the pin function is specified to a general purpose I/O. Port 6 Register (PORT6) PORT6 shows the pin states.
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Section 10 I/O Ports 10.6.4 Pin Functions Port 6 pins also function as 8-bit timer I/Os, interrupt inputs, and DMAC I/Os. The correspondence between the register specification and the pin functions is shown below. • P65/TMO1/DACK1/IRQ13 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit SAE1 in DMABCRH, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit P65DDR, and bit ITS13 in ITSR.
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Section 10 I/O Ports • P63/TMCI1/TEND1/IRQ11 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit TEE1 in DMATCR of the DMAC, bit P63DDR, and bit ITS11 in ITSR. TEE1 0 DMACS — P63DDR Pin function 1 1 0 1 0 P63 input P63 output P63 input 0 1 P63 output 1 IRQ11 interrupt input* TMCI1 input* — TEND1 output 2 Notes: 1. IRQ11 interrupt input when ITS11 = 0. 2.
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Section 10 I/O Ports • P61/TMRI1/DREQ1/IRQ9 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit P61DDR, and bit ITS9 in ITSR. P61DDR Pin function 0 1 P61 input P61 output 1 TMRI1 input* 2 DREQ1 input* IRQ9 interrupt input* 3 Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_1 should be set to 1. 2. DREQ1 input when DMAKS = 0. 3. IRQ9 interrupt input when ITS9 = 0.
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Section 10 I/O Ports 10.7 Port 7 Port 7 is a 6-bit I/O port that also has other functions. The port 7 has the following registers. For details on the port function control register 2, refer to section 10.3.5, Port Function Control Register 2 (PFCR2). • Port 7 data direction register (P7DDR) • Port 7 data register (P7DR) • Port 7 register (PORT7) • Port function control register 2 (PFCR2) 10.7.
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Section 10 I/O Ports 10.7.2 Port 7 Data Register (P7DR) P7DR stores output data for the port 7 pins. Bit Bit Name Initial Value R/W 7, 6 — All 0 — Description Reserved These bits are always read as 0 and cannot be modified. 5 P75DR 0 R/W 4 P74DR 0 R/W 3 P73DR 0 R/W 2 P72DR 0 R/W 1 P71DR 0 R/W 0 P70DR 0 R/W 10.7.3 Output data for a pin is stored when the pin function is specified to a general purpose I/O. Port 7 Register (PORT7) PORT7 shows the pin states.
PAGE 526
Section 10 I/O Ports 10.7.4 Pin Functions Port 7 pins also function as DMAC I/Os and EXDMAC I/Os. The correspondence between the register specification and the pin functions is shown below. • P75/DACK1/EDACK1 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit SAE1 in DMABCRH, bit AMS in EDMDR_1, and bit P75DDR.
PAGE 527
Section 10 I/O Ports • P74/DACK0/EDACK0 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit SAE0 in DMABCRH, bit AMS in EDMDR_0, and bit P74DDR.
PAGE 528
Section 10 I/O Ports Modes 3* (EXPE = 0), 7 (EXPE = 0) ETENDE — TEE1 0 DMACS — P73DDR Pin function Note: * 1 0 1 0 1 0 1 — P73 input P73 output P73 input P73 output TEND1 output Only in H8S/2678R Group. • P72/TEND0/ETEND0 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit TEE0 in DMATCR of the DMAC, bit ETENDE in EDMDR_0 of the EXDMAC, and bit P72DDR.
PAGE 529
Section 10 I/O Ports • P71/DREQ1/EDREQ1 The pin function is switched as shown below according to the combination of bit P71DDR and bit DMACS in PFCR2. P71DDR 0 Pin function 1 P71 input P71 output DREQ1 input* EDREQ1 input Note: * DREQ1 input when DMACS = 1. • P70/DREQ0/EDREQ0 The pin function is switched as shown below according to the combination of bit P70DDR and bit DMACS in PFCR2. P70DDR 0 Pin function 1 P70 input P70 output DREQ0 input* EDREQ0 input Note: * DREQ0 input when DMACS = 1.
PAGE 530
Section 10 I/O Ports 10.8 Port 8 Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers. • Port 8 data direction register (P8DDR) • Port 8 data register (P8DR) • Port 8 register (PORT8) 10.8.1 Port 8 Data Direction Register (P8DDR) The individual bits of P8DDR specify input or output for the pins of port 8. P8DDR cannot be read; if it is, an undefined value will be read.
PAGE 531
Section 10 I/O Ports 10.8.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Bit Name Initial Value R/W 7, 6 — All 0 — Description Reserved These bits are always read as 0 and cannot be modified. 5 P85DR 0 R/W 4 P84DR 0 R/W 3 P83DR 0 R/W 2 P82DR 0 R/W 1 P81DR 0 R/W 0 P80DR 0 R/W 10.8.3 Output data for a pin is stored when the pin function is specified to a general purpose I/O. Port 8 Register (PORT8) PORT8 shows the pin states.
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Section 10 I/O Ports 10.8.4 Pin Functions Port 8 pins also function as interrupt inputs and EXDMAC I/Os. The correspondence between the register specification and the pin functions is shown below. • P85/(IRQ5)/EDACK3 The pin function is switched as shown below according to the combination of bit AMS in EDMDR_3 of the EXDMAC, bit P85DDR, and bit ITS5 in ITSR.
PAGE 533
Section 10 I/O Ports Modes 3* (EXPE = 0), 7 (EXPE = 0) 2 AMS — P84DDR 0 Pin function 1 P84 input P84 output 1 * IRQ4 interrupt input Notes: 1. IRQ4 input when ITS4 = 1. 2. Only in H8S/2678R Group. • P83/(IRQ3)/ETEND3 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_3 of the EXDMAC, bit P83DDR, and bit ITS3 in ITSR.
PAGE 534
Section 10 I/O Ports • P82/(IRQ2)/ETEND2 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) 2 ETENDE 0 P82DDR Pin function 1 0 1 — P82 input P82 output ETEND2 output IRQ2 interrupt input* 1 Modes 3* (EXPE = 0), 7 (EXPE = 0) 2 ETENDE — P82DDR 0 Pin function 1 P82 input P82 output IRQ2 interrupt input* 1 Notes: 1. IRQ2 input when ITS2 = 1. 2.
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Section 10 I/O Ports • P80/(IRQ0)/EDREQ2 The pin function is switched as shown below according to the combination of bit P80DDR and bit ITS0 in ITSR. P80DDR Pin function 0 1 P80 input P80 output EDREQ2 input IRQ0 interrupt input* Note: 10.9 * IRQ0 input when ITS0 = 1. Port A Port A is an 8-bit I/O port that also has other functions. The port A has the following registers.
PAGE 536
Section 10 I/O Ports 10.9.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PA7DDR 0 W • 6 PA6DDR 0 W 5 PA5DDR 0 W Pins PA4 to PA0 are address outputs regardless of the PADDR settings.
PAGE 537
Section 10 I/O Ports 10.9.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description 7 PA7DR 0 R/W 6 PA6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PA5DR 0 R/W 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W 10.9.3 Port A Register (PORTA) PORTA shows port A pin states. PORTA cannot be modified.
PAGE 538
Section 10 I/O Ports 10.9.4 Port A Pull-Up MOS Control Register (PAPCR) PAPCR controls the input pull-up MOS function. Bits 7 to 5 are valid in modes 1, 2, 5, and 6, and all the bits are valid in modes 3*, 4, and 7. Note: * Only in H8S/2678R Group. Bit Bit Name Initial Value R/W Description 7 PA7PCR 0 R/W 6 PA6PCR 0 R/W When a pin function is specified to an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
PAGE 539
Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 7 A23E 1 R/W Address 23 Enable Enables or disables output for address output 23 (A23). 0: DR output when PA7DDR = 1 1: A23 output when PA7DDR = 1 6 A22E 1 R/W Address 22 Enable Enables or disables output for address output 22 (A22). 0: DR output when PA6DDR = 1 1: A22 output when PA6DDR = 1 5 A21E 1 R/W Address 21 Enable Enables or disables output for address output 21 (A21).
PAGE 540
Section 10 I/O Ports 10.9.7 Pin Functions Port A pins also function as address outputs. The correspondence between the register specification and the pin functions is shown below. • PA7/A23, PA6/A22, PA5/A21 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A23E to A21E, and bit PADDR.
PAGE 541
Section 10 I/O Ports 10.9.8 Port A Input Pull-Up MOS States Port A has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used by pins PA7 to PA5 in modes 1, 2, 5, and 6, and by all pins in modes 3*, 4, and 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. Table 10.2 summarizes the input pull-up MOS states. Table 10.
PAGE 542
Section 10 I/O Ports 10.10.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PB7DDR 0 W • 6 PB6DDR 0 W 5 PB5DDR 0 W Port B pins are address outputs regardless of the PBDDR settings.
PAGE 543
Section 10 I/O Ports 10.10.3 Port B Register (PORTB) PORTB shows port B pin states. PORTB cannot be modified. Bit Bit Name Initial Value R/W Description 7 PB7 Undefined* R 6 PB6 R 5 PB5 Undefined* Undefined* If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read.
PAGE 544
Section 10 I/O Ports 10.10.5 Pin Functions Port B pins also function as address outputs. The correspondence between the register specification and the pin functions is shown below. • PB7/A15, PB6/A14, PB5/A13, PB4/A12, PB3/A11, PB2/A10, PB1/A9, PB0/A8 The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PBDDR.
PAGE 545
Section 10 I/O Ports 10.11 Port C Port C is an 8-bit I/O port that also has other functions. The port C has the following registers. • Port C data direction register (PCDDR) • Port C data register (PCDR) • Port C register (PORTC) • Port C pull-up MOS control register (PCPCR) 10.11.1 Port C Data Direction Register (PCDDR) The individual bits of PCDDR specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.
PAGE 546
Section 10 I/O Ports 10.11.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Bit Name Initial Value R/W Description 7 PC7DR 0 R/W 6 PC6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W 10.11.3 Port C Register (PORTC) PORTC is shows port C pin states. PORTC cannot be modified.
PAGE 547
Section 10 I/O Ports 10.11.4 Port C Pull-Up MOS Control Register (PCPCR) PCPCR controls the on/off state of input pull-up MOS of port C. PCPCR is valid in modes 3*, 4, and 7. Bit Bit Name Initial Value R/W Description 7 PC7PCR 0 R/W 6 PC6PCR 0 R/W When a pin function is specified to an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
PAGE 548
Section 10 I/O Ports 10.11.6 Port C Input Pull-Up MOS States Port C has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 3*, 4, and 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 3*, 4, and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.4 summarizes the input pull-up MOS states. Table 10.
PAGE 549
Section 10 I/O Ports 10.12.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PAGE 550
Section 10 I/O Ports 10.12.3 Port D Register (PORTD) PORTD shows port D pin states. PORTD cannot be modified. Bit Bit Name Initial Value R/W Description 7 PD7 Undefined* R 6 PD6 R 5 PD5 Undefined* Undefined* If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read.
PAGE 551
Section 10 I/O Ports 10.12.5 Pin Functions Port D pins also function as data I/Os. The correspondence between the register specification and the pin functions is shown below. • PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8 The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PDDDR. Operating mode 3*, 7 1, 2, 4, 5, 6 EXPE — PDDDR — 0 1 — Data I/O PD input PD output Data I/O Pin function Note: * 0 1 Only in H8S/2678R Group.
PAGE 552
Section 10 I/O Ports 10.13 Port E Port E is an 8-bit I/O port that also has other functions. The port E has the following registers. • Port E data direction register (PEDDR) • Port E data register (PEDR) • Port E register (PORTE) • Port E pull-up MOS control register (PEPCR) 10.13.1 Port E Data Direction Register (PEDDR) The individual bits of PEDDR specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
PAGE 553
Section 10 I/O Ports 10.13.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Bit Name Initial Value R/W Description 7 PE7DR 0 R/W 6 PE6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W 10.13.3 Port E Register (PORTE) PORTE shows port E pin states. PORTE cannot be modified.
PAGE 554
Section 10 I/O Ports 10.13.4 Port E Pull-up Control Register (PEPCR) PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus mode. Bit Bit Name Initial Value R/W Description 7 PE7PCR 0 R/W 6 PE6PCR 0 R/W 5 PE5PCR 0 R/W 4 PE4PCR 0 R/W 3 PE3PCR 0 R/W 2 PE2PCR 0 R/W 1 PE1PCR 0 R/W 0 PE0PCR 0 R/W When the pin is in its input state, the input pull-up MOS of the input pin is on when the corresponding bit is set to 1. 10.13.
PAGE 555
Section 10 I/O Ports 10.13.6 Port E Input Pull-Up MOS States Port E has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in 8-bit bus mode. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.6 summarizes the input pull-up MOS states. Table 10.
PAGE 556
Section 10 I/O Ports 10.14.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PF7DDR 1 1/0* W • 6 PF6DDR 0 W 5 PF5DDR 0 W Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0.
PAGE 557
Section 10 I/O Ports Bit Bit Name Initial Value R/W Description • Modes 3* and 7 (when EXPE = 0) 2 Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Pins PF6 to PF0 are I/O ports, and their functions can be switched with PFDDR. Notes: 1. PF7DDR is initialized to 1 in modes 1, 2, 4, 5, and 6, and to 0 in mode 7. 2. Only in H8S/2678R Group. 10.14.
PAGE 558
Section 10 I/O Ports 10.14.3 Port F Register (PORTF) PORTF shows port F pin states. PORTF cannot be modified. Bit Bit Name Initial Value R/W Description 7 PF7 Undefined* R 6 PF6 R 5 PF5 Undefined* Undefined* If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read.
PAGE 559
Section 10 I/O Ports • PF6/AS The pin function is switched as shown below according to the operating mode, bit EXPE, bit PF6DDR, and bit ASOE. Operating mode 3*, 7 1, 2, 4, 5, 6 EXPE — 0 1 PF6DDR — 0 1 0 1 — 0 1 AS output PF6 input PF6 output PF6 input PF6 output AS output PF6 input PF6 output Pin function Note: * 0 1 ASOE — 1 0 Only in H8S/2678R Group. • PF5/RD The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PF5DDR.
PAGE 560
Section 10 I/O Ports • PF3/LWR The pin function is switched as shown below according to the operating mode, bit EXPE, bit PF3DDR, and bit LWROE. Operating mode 3*, 7 1, 2, 4, 5, 6 EXPE — 0 1 PF3DDR — 0 1 0 1 — 0 1 LWR output PF3 input PF3 output PF3 input PF3 output LWR output PF3 input PF3 output Pin function Note: * 0 1 LWROD — 1 0 Only in H8S/2678R Group.
PAGE 561
Section 10 I/O Ports • PF1/UCAS/DQMU* /IRQ14 2 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR.
PAGE 562
Section 10 I/O Ports 10.15 Port G Port G is a 7-bit I/O port that also has other functions. The port G has the following registers. • Port G data direction register (PGDDR) • Port G data register (PGDR) • Port G register (PORTG) • Port Function Control Register 0 (PFCR0) 10.15.1 Port G Data Direction Register (PGDDR) The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be read; if it is, an undefined value will be read. Rev. 3.
PAGE 563
Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 7 — 0 — Reserved If read, it returns an undefined value. 6 PG6DDR 0 W • Pins PG6 to PG4 function as bus control input/output pins (BREQO, BACK, and BREQ) when the appropriate bus controller settings are made. Otherwise, these pins are I/O ports, and their functions can be switched with PGDDR.
PAGE 564
Section 10 I/O Ports 10.15.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Bit Name Initial Value R/W Description 7 — 0 — Reserved This bit is always read as 0, and cannot be modified. 6 PG6DR 0 R/W 5 PG5DR 0 R/W 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 PG0DR 0 R/W An output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.15.3 Port G Register (PORTG) PORTG shows port G pin states.
PAGE 565
Section 10 I/O Ports 10.15.4 Port Function Control Register 0 (PFCR0) PFCR0 performs I/O port control. Bit Bit Name Initial Value R/W Description 7 CS7E 0 R/W CS7 to CS0 Enable 6 CS6E 0 R/W 5 CS5E 0 R/W These bits enable or disable the corresponding CSn output. 4 CS4E 0 R/W 3 CS3E 0 R/W 2 CS2E 0 R/W 1 CS1E 0 R/W 0 CS0E 0 R/W 0: Pin is designated as I/O port 1: Pin is designated as CSn output pin (n = 7 to 0) 10.15.
PAGE 566
Section 10 I/O Ports • PG5/BACK The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, and bit PG5DDR. Operating mode EXPE — BRLE 0 0 PG5DDR Pin function Note: 3*, 7 1, 2, 4, 5, 6 * 1 1 — 0 1 0 1 — 0 1 0 1 — PG5 input PG5 output BACK output PG5 input PG5 output PG5 input PG5 output BACK output Only in H8S/2678R Group.
PAGE 567
Section 10 I/O Ports • PG3/CS3/RAS3*/CAS*, PG2/CS2/RAS2*/RAS* The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, bit CSnE, and bits RMTS2 to RMTS0.
PAGE 568
Section 10 I/O Ports 10.16 Port H Port H is a 4-bit I/O port that also has other functions. The port H has the following registers. For details on the port function control register 0, refer to section 10.15.4, Port Function Control Register 0 (PFCR0), and for details on the port function control register 2, refer to section 10.3.5, Port Function Control Register 2 (PFCR2).
PAGE 569
Section 10 I/O Ports 10.16.1 Port H Data Direction Register (PHDDR) The individual bits of PHDDR specify input or output for the pins of port H. PHDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 — Reserved 3 PH3DDR 0 W 2 PH2DDR 0 W 1 PH1DDR 0 W 0 PH0DDR 0 W If these bits are read, they will return an undefined value.
PAGE 570
Section 10 I/O Ports 10.16.2 Port H Data Register (PHDR) PHDR stores output data for the port H pins. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 — Reserved 3 PH3DR 0 R/W 2 PH2DR 0 R/W 1 PH1DR 0 R/W 0 PH0DR 0 R/W These bits are reserved; they are always read as 0 and cannot be modified. Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.16.3 Port H Register (PORTH) PORTH shows port H pin states. PORTH cannot be modified.
PAGE 571
Section 10 I/O Ports 10.16.4 Pin Functions Port H pins also function as bus control signal I/Os and external interrupt inputs. The correspondence between the register specification and the pin functions is shown below. • PH3/CS7/OE/CKE* /(IRQ7) 2 The pin function is switched as shown below according to the operating mode, bit EXPE, bit OEE, bit OES, bit CS7E, and bit PH3DDR.
PAGE 572
Section 10 I/O Ports • PH1/CS5/RAS5*/SDRAMφ* The pin function is switched as shown below according to the operating mode, DCTL pin, bit EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR.
PAGE 573
Section 11 16-Bit Timer Pulse Unit (TPU) Section 11 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 11.1 and figure 11.1, respectively. 11.
PAGE 574
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 575
Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC TGRA_0 activation compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input captu
PAGE 576
TGRD TGRB TGRC TGRB A/D conversion start request signal TGRD TGRB TGRB TGRB PPG output trigger signal Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 11.1 Block Diagram of TPU Rev. 3.
PAGE 577
Section 11 16-Bit Timer Pulse Unit (TPU) 11.2 Input/Output Pins Table 11.
PAGE 578
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3 Register Descriptions The TPU has the following registers in each channel.
PAGE 579
Section 11 16-Bit Timer Pulse Unit (TPU) • Timer interrupt enable register_3 (TIER_3) • Timer status register_3 (TSR_3) • Timer counter_3 (TCNT_3) • Timer general register A_3 (TGRA_3) • Timer general register B_3 (TGRB_3) • Timer general register C_3 (TGRC_3) • Timer general register D_3 (TGRD_3) • Timer control register_4 (TCR_4) • Timer mode register_4 (TMDR_4) • Timer I/O control register _4 (TIOR_4) • Timer interrupt enable register_4 (TIER_4) • Timer status register_4 (TSR_4) • Timer counter_4 (TCNT_
PAGE 580
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7 6 5 CCLR2 CCLR1 CCLR0 0 0 0 R/W R/W R/W Counter Clear 2 to 0 4 3 CKEG1 CKEG0 0 0 R/W R/W Clock Edge 1 and 0 These bits select the TCNT counter clearing source.
PAGE 581
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 582
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.5 TPSC2 to TPSC0 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 1 1 0 1 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input Table 11.
PAGE 583
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 584
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 585
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.2 Timer Mode Register (TMDR) TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7, 6 — All 1 — Reserved These bits are always read as 1 and cannot be modified.
PAGE 586
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.11 MD3 to MD0 Bit 3 1 MD3* Bit 2 2 MD2* Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 x — 1 1 0 1 1 x x Legend: x: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3.
PAGE 587
Section 11 16-Bit Timer Pulse Unit (TPU) TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Initial Value Bit Bit Name 7 6 5 4 IOB3 IOB2 IOB1 IOB0 3 2 1 0 IOA3 IOA2 IOA1 IOA0 R/W Description 0 0 0 0 R/W R/W R/W R/W I/O Control B3 to B0 0 0 0 0 R/W R/W R/W R/W I/O Control A3 to A0 R/W Description Specify the function of TGRB. For details, see tables 11.12, 11.14, 11.15, 11.16, 11.18, and 11.19. Specify the function of TGRA. For details, see tables 11.20, 11.22, 11.23, 11.24, 11.26, and 11.27.
PAGE 588
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 589
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 590
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 591
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 592
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 593
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 594
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 595
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 596
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 597
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 598
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 599
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 600
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 601
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 602
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 603
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 604
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.4 Timer Interrupt Enable Register (TIER) TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE 0 R/W A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
PAGE 605
Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.5 Timer Status Register (TSR) TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.
PAGE 607
Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 3 TGFD 0 R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
PAGE 608
Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match.
PAGE 609
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 11.3.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description 7, 6 — All 0 R/W Reserved 5 4 3 2 1 0 SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W These bits should always be written with 0.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.4 Operation 11.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
PAGE 612
Section 11 16-Bit Timer Pulse Unit (TPU) 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt.
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Section 11 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 11.4 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. 1. Example of setting procedure for waveform output by compare match Figure 11.5 shows an example of the setting procedure for waveform output by a compare match.
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Section 11 16-Bit Timer Pulse Unit (TPU) 2. Examples of waveform output operation Figure 11.6 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA No change TIOCB No change 0 output Figure 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
PAGE 616
Section 11 16-Bit Timer Pulse Unit (TPU) 2. Example of input capture operation Figure 11.9 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
PAGE 617
Section 11 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Setting Procedure: Figure 11.10 shows an example of the synchronous operation setting procedure.
PAGE 618
Section 11 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 11.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2.
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Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.28 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 TGRA_3 TGRC_3 TGRB_3 TGRD_3 3 • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 11.12.
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Section 11 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Setting Procedure: Figure 11.14 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. Buffer operation [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. Set buffer operation [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count [3] Select TGR function Figure 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation: 1. When TGR is an output compare register Figure 11.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
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Section 11 16-Bit Timer Pulse Unit (TPU) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA H'0532 TGRA TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 11.16 Example of Buffer Operation (2) 11.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
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Section 11 16-Bit Timer Pulse Unit (TPU) Example of Cascaded Operation Setting Procedure: Figure 11.17 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading [1] Start count [2] [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Figure 11.
PAGE 624
Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 FFFD TCNT_1 FFFE FFFF 0000 0000 0001 0002 0001 0000 0001 FFFF 0000 Figure 11.19 Example of Cascaded Operation (2) 11.4.
PAGE 625
Section 11 16-Bit Timer Pulse Unit (TPU) • PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs.
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Section 11 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 11.20 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
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Section 11 16-Bit Timer Pulse Unit (TPU) TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 11.21 Example of PWM Mode Operation (1) Figure 11.22 shows an example of PWM mode 2 operation.
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Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
PAGE 630
Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 11.25 shows an example of phase counting mode 1 operation, and table 11.32 summarizes the TCNT up/down-count conditions.
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Section 11 16-Bit Timer Pulse Unit (TPU) 2. Phase counting mode 2 Figure 11.26 shows an example of phase counting mode 2 operation, and table 11.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.26 Example of Phase Counting Mode 2 Operation Table 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) 3. Phase counting mode 3 Figure 11.27 shows an example of phase counting mode 3 operation, and table 11.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 11.27 Example of Phase Counting Mode 3 Operation Table 11.
PAGE 633
Section 11 16-Bit Timer Pulse Unit (TPU) 4. Phase counting mode 4 Figure 11.28 shows an example of phase counting mode 4 operation, and table 11.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 11.28 Example of Phase Counting Mode 4 Operation Table 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example: Figure 11.29 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
PAGE 635
Section 11 16-Bit Timer Pulse Unit (TPU) 11.5 Interrupt Sources There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
PAGE 636
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 637
Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
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Section 11 16-Bit Timer Pulse Unit (TPU) In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 11.9 Operation Timing 11.9.1 Input/Output Timing TCNT Count Timing: Figure 11.30 shows TCNT count timing in internal clock operation, and figure 11.31 shows TCNT count timing in external clock operation. φ Internal clock Rising edge Falling edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the (TIOC pin) TCNT input clock is generated. Figure 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 11.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 11.35 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 11.34 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal TCNT N H'0000 N TGR Figure 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 11.36 and 11.37 show the timings in buffer operation. φ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 11.36 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 11.37 Buffer Operation Timing (Input Capture) Rev. 3.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.9.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 11.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 11.38 TGI Interrupt Timing (Compare Match) Rev. 3.
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Section 11 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture: Figure 11.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. φ Input capture signal TCNT TGR N N TGF flag TGI interrupt Figure 11.39 TGI Interrupt Timing (Input Capture) Rev. 3.
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Section 11 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing: Figure 11.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 11.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.42 shows the timing for status flag clearing by the CPU, and figure 11.43 shows the timing for status flag clearing by the DTC or DMAC. TSR write cycle T1 T2 φ Address TSR address Write signal Status flag Interrupt request signal Figure 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.10 Usage Notes 11.10.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 11.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.
PAGE 647
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= φ (N + 1) Where f: Counter frequency φ: Operating frequency N: TGR set value 11.10.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.46 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 11.46 Contention between TCNT Write and Increment Operations Rev. 3.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 11.47 shows the timing in this case. TGR write cycle T1 T2 φ TGR address Address Write signal Compare match signal Prohibited TCNT N N+1 TGR N M TGR write data Figure 11.
PAGE 650
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 11.48 shows the timing in this case. TGR write cycle T1 T2 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11.49 shows the timing in this case. TGR read cycle T1 T2 φ TGR address Address Read signal Input capture signal TGR X Internal data bus M M Figure 11.49 Contention between TGR Read and Input Capture Rev. 3.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.50 shows the timing in this case. TGR write cycle T1 T2 φ Address TGR address Write signal Input capture signal TCNT M M TGR Figure 11.50 Contention between TGR Write and Input Capture Rev. 3.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.10 Contention between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.51 shows the timing in this case. Buffer register write cycle T1 T2 φ Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 11.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.52 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clearing signal TGF Prohibited TCFV Figure 11.
PAGE 655
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.53 shows the operation timing when there is contention between TCNT write and overflow.
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Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 3.
PAGE 657
Section 12 Programmable Pulse Generator (PPG) Section 12 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. The block diagram of PPG is shown in figure 12.1 12.
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Section 12 Programmable Pulse Generator (PPG) Compare match signals Control logic PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Legend: PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL NDERH NDERL PMR PCR Pulse output pins, group 3 PODRH NDRH PODRL NDRL Pulse output pins, group 2 Pulse output pins, group 1 Pulse output pins, group 0 : PPG output mode register : PPG output control register : Next data enable register H : Next data enable register L : Next data register H : Next
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Section 12 Programmable Pulse Generator (PPG) 12.2 Input/Output Pins Table 12.1 shows the PPG pin configuration. Table 12.1 Pin Configuration Pin Name I/O Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output PO10 Output PO9 Output PO8 Output PO7 Output PO6 Output PO5 Output PO4 Output PO3 Output PO2 Output PO1 Output PO0 Output 12.
PAGE 660
Section 12 Programmable Pulse Generator (PPG) 12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1.
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Section 12 Programmable Pulse Generator (PPG) 12.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified.
PAGE 662
Section 12 Programmable Pulse Generator (PPG) 12.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
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Section 12 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 3 NDR11 0 R/W Next Data Register 11 to 8 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. These bits are always read as 1 and cannot be modified.
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Section 12 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 3 NDR3 0 R/W Next Data Register 3 to 0 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 12.3.4 These bits are always read as 1 and cannot be modified. PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis.
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Section 12 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 1 G0CMS1 1 R/W Group 0 Compare Match Select 1 and 0 0 G0CMS0 1 R/W Select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 12.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group.
PAGE 666
Section 12 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 4 G0INV 1 R/W Group 0 Inversion Selects direct output or inverted output for pulse output group 0. 0: Inverted output 1: Direct output 3 G3NOV 0 R/W Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3.
PAGE 667
Section 12 Programmable Pulse Generator (PPG) 12.4 Operation Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
PAGE 668
Section 12 Programmable Pulse Generator (PPG) 12.4.1 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ N TCNT TGRA N+1 N Compare match A signal n NDRH PODRH PO8 to PO15 m n m n Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) Rev. 3.
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Section 12 Programmable Pulse Generator (PPG) 12.4.2 Sample Setup Procedure for Normal Pulse Output Figure 12.4 shows a sample procedure for setting up normal pulse output.
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Section 12 Programmable Pulse Generator (PPG) 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value Compare match TCNT TGRA H'0000 Time 80 NDRH PODRH 00 C0 80 40 C0 60 40 20 60 30 20 10 30 18 10 08 18 88 08 80 88 C0 80 40 C0 PO15 PO14 PO13 PO12 PO11 Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) 1.
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Section 12 Programmable Pulse Generator (PPG) If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. 12.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: • NDR bits are always transferred to PODR bits at compare match A. • At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 12.
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Section 12 Programmable Pulse Generator (PPG) Compare match A Compare match B Write to NDR Write to NDR NDR PODR 0 output 0/1 output Write to NDR Do not write here to NDR here 0 output 0/1 output Do not write to NDR here Write to NDR here Figure 12.7 Non-Overlapping Operation and NDR Write Timing Rev. 3.
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Section 12 Programmable Pulse Generator (PPG) 12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output.
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Section 12 Programmable Pulse Generator (PPG) 12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 12.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRH Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.
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Section 12 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2.
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Section 12 Programmable Pulse Generator (PPG) 12.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.9. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRL Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.
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Section 12 Programmable Pulse Generator (PPG) 12.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 12.11 shows the timing of this output. φ TIOC pin Input capture signal NDR N PODR M PO M N N Figure 12.11 Pulse Output Triggered by Input Capture (Example) 12.
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Section 12 Programmable Pulse Generator (PPG) Rev. 3.
PAGE 679
Section 13 8-Bit Timers (TMR) Section 13 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 13.
PAGE 680
Section 13 8-Bit Timers (TMR) Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
PAGE 681
Section 13 8-Bit Timers (TMR) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the 8-bit timer. Table 13.
PAGE 682
Section 13 8-Bit Timers (TMR) 13.3.1 Timer Counter (TCNT) TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a clock. TCNT can be cleared by an external reset input or by a compare match signal A or B. Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1.
PAGE 683
Section 13 8-Bit Timers (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts. Bit Bit Name Initial Value R/W 7 CMIEB 0 R/W Description Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1.
PAGE 684
Section 13 8-Bit Timers (TMR) Table 13.
PAGE 685
Section 13 8-Bit Timers (TMR) 13.3.5 Timer Control/Status Register (TCSR) TCSR displays status flags, and controls compare match output.
PAGE 686
Section 13 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 3 2 OS3 OS2 0 0 R/W R/W Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs.
PAGE 687
Section 13 8-Bit Timers (TMR) TCSR_1 Bit 7 Bit Name CMFB Initial Value R/W Description 0 R/(W)* Compare Match Flag B [Setting condition] Set when TCNT matches TCORB [Clearing conditions] 6 CMFA 0 R/(W)* • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 Compare Match Flag A [Setting condition] Set when TCNT matches TCORA [Clearing conditions] 5 OVF 0 R/(W)* • Cleared by reading CMFA when CMFA = 1
PAGE 688
Section 13 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 3 2 OS3 OS2 0 0 R/W R/W Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs.
PAGE 689
Section 13 8-Bit Timers (TMR) TCNT H'FF Counter clear TCORA TCORB H'00 TMO Figure 13.2 Example of Pulse Output 13.5 Operation Timing 13.5.1 TCNT Incrementation Timing Figure 13.3 shows the count timing for internal clock input. Figure 13.4 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges.
PAGE 690
Section 13 8-Bit Timers (TMR) φ External clock input pin Clock input to TCNT TCNT N–1 N N+1 Figure 13.4 Count Timing for External Clock Input 13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated.
PAGE 691
Section 13 8-Bit Timers (TMR) 13.5.3 Timing of Timer Output when Compare-Match Occurs When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Figure 13.6 shows the timing when the output is set to toggle at compare match A. φ Compare match A signal Timer output pin Figure 13.6 Timing of Timer Output 13.5.4 Timing of Compare Match Clear TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.
PAGE 692
Section 13 8-Bit Timers (TMR) 13.5.5 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 13.8 shows the timing of this operation. φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 13.8 Timing of Clearance by External Reset 13.5.
PAGE 693
Section 13 8-Bit Timers (TMR) 13.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). In this case, the timer operates as below. 13.6.
PAGE 694
Section 13 8-Bit Timers (TMR) 13.7 Interrupts 13.7.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 13.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 13.
PAGE 695
Section 13 8-Bit Timers (TMR) 13.8 Usage Notes 13.8.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 13.10 shows this operation. TCNT write cycle by CPU T1 T2 φ TCNT address Address Internal write signal Counter clear signal TCNT N H'00 Figure 13.10 Contention between TCNT Write and Clear Rev. 3.
PAGE 696
Section 13 8-Bit Timers (TMR) 13.8.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 13.11 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.11 Contention between TCNT Write and Increment Rev. 3.
PAGE 697
Section 13 8-Bit Timers (TMR) 13.8.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 13.12. TCOR write cycle by CPU T1 T2 φ TCOR address Address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Prohibited Figure 13.12 Contention between TCOR Write and Compare Match Rev. 3.
PAGE 698
Section 13 8-Bit Timers (TMR) 13.8.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13.4. Table 13.4 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 13.8.
PAGE 699
Section 13 8-Bit Timers (TMR) Table 13.5 Switching of Internal Clock and TCNT Operation No.
PAGE 700
Section 13 8-Bit Timers (TMR) No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. 13.8.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
PAGE 701
Section 14 Watchdog Timer Section 14 Watchdog Timer The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows.
PAGE 702
Section 14 Watchdog Timer WOVI (interrupt request signal) Clock WDTOVF Internal reset signal* Clock select Reset control RSTCSR TCNT φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock sources TSCR Module bus Bus interface Internal bus Overflow Interrupt control WDT Legend: : Timer control/status register TCSR : Timer counter TCNT RSTCSR : Reset control/status register Note: * An internal reset signal can be generated by the register setting. Figure 14.
PAGE 703
Section 14 Watchdog Timer 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. Bit 7 Bit Name OVF Initial Value R/W Description 0 R/(W)* Overflow Flag Indicates that TCNT has overflowed in interval timer mode. Only a write of 0 is permitted, to clear the flag.
PAGE 704
Section 14 Watchdog Timer Bit Bit Name Initial Value R/W Description 4, 3 — All 1 — Reserved These bits are always read as 1 and cannot be modified. 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to TCNT. The overflow frequency for φ = 20 MHz is enclosed in parentheses. 000: Clock φ/2 (frequency: 25.6 µs) 001: Clock φ/64 (frequency: 819.2 µs) 010: Clock φ/128 (frequency: 1.6 ms) 011: Clock φ/512 (frequency: 6.
PAGE 705
Section 14 Watchdog Timer 14.3.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Bit 7 Bit Name WOVF Initial Value R/W Description 0 R/(W)* Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode.
PAGE 706
Section 14 Watchdog Timer 14.4 Operation 14.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs.
PAGE 707
Section 14 Watchdog Timer TCNT count Overflow H'FF Time H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT WDTOVF signal 132 states*2 Internal reset signal*1 518 states Legend: WT/IT : Timer mode select bit TME : Timer enable bit Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0. Figure 14.2 Operation in Watchdog Timer Mode 14.4.
PAGE 708
Section 14 Watchdog Timer TCNT count Overflow H'FF Overflow Overflow Overflow Time H'00 WOVI WT/IT=0 TME=1 WOVI WOVI WOVI Legend: WOVI: Interval timer interrupt request generation Figure 14.3 Operation in Interval Timer Mode 14.5 Interrupt Source During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine.
PAGE 709
Section 14 Watchdog Timer Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 14.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition. To write to RSTCSR, execute a word transfer instruction for address H'FFBE.
PAGE 710
Section 14 Watchdog Timer 14.6.2 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this operation. TCNT write cycle T1 T2 Next cycle φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.5 Contention between TCNT Write and Increment 14.6.
PAGE 711
Section 14 Watchdog Timer 14.6.5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag. 14.6.
PAGE 712
Section 14 Watchdog Timer Rev. 3.
PAGE 713
Section 15 Serial Communication Interface (SCI, IrDA) Section 15 Serial Communication Interface (SCI, IrDA) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
PAGE 714
Section 15 Serial Communication Interface (SCI, IrDA) • Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error • Average transfer rate generator (only for H8S/2678R Group): The following transfer rate can be selected (SCI_2 only) 115.152 or 460.606 kbps at 10.667-MHz operation 115.196, 460.
PAGE 715
Bus interface Section 15 Serial Communication Interface (SCI, IrDA) Module data bus RDR RxD RSR SCMR SSR SCR SMR SEMR* TDR TSR BRR φ Baud rate generator Transmission/ reception control TxD Parity generation φ/4 φ/16 φ/64 Clock Parity check External clock SCK Internal data bus TEI TXI RXI ERI Legend: RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status
PAGE 716
Section 15 Serial Communication Interface (SCI, IrDA) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the serial communication interface. Table 15.
PAGE 717
Section 15 Serial Communication Interface (SCI, IrDA) • Receive data register_1 (RDR_1) • Transmit data register_1 (TDR_1) • Serial mode register_1 (SMR_1) • Serial control register_1 (SCR_1) • Serial status register_1 (SSR_1) • Smart card mode register_1 (SCMR_1) • Bit rate register_1 (BRR_1) • Receive shift register_2 (RSR_2) • Transmit shift register_2 (TSR_2) • Receive data register_2 (RDR_2) • Transmit data register_2 (TDR_2) • Serial mode register_2 (SMR_2) • Serial control register_2 (SCR_2) • Seria
PAGE 718
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission.
PAGE 719
Section 15 Serial Communication Interface (SCI, IrDA) Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit Bit Name Initial Value R/W Description 7 C/A 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) of TDR is not transmitted in transmission.
PAGE 720
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 CKS1 0 R/W Clock Select 1 and 0: 0 CKS0 0 R/W These bits select the clock source for the on-chip baud rate generator.
PAGE 721
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on setting this bit in Smart Card interface mode, refer to section 15.7.2, Data Format (Except for Block Transfer Mode).
PAGE 722
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.6 Serial Control Register (SCR) SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer/receive clock source. For details on interrupt requests, refer to section 15.9, Interrupts Sources. Some bit functions of SCR differ in normal serial communication interface mode and Smart Card interface mode.
PAGE 723
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 1 and 0 0 CKE0 0 R/W Selects the clock source and SCK pin function. Asynchronous mode 00: On-chip baud rate generator SCK pin functions as I/O port 01: On-chip baud rate generator (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1X: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.
PAGE 724
Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled.
PAGE 725
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ in normal serial communication interface mode and Smart Card interface mode.
PAGE 726
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 ORER 0 R/(W)* Overrun Error [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 4 FER 0 R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked.
PAGE 727
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 1 MPB 0 R Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT sets the multiprocessor bit to be added to the transmit data. Note: * Only 0 can be written, to clear the flag.
PAGE 728
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 ORER 0 R/(W)* Overrun Error [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 4 ERS 0 R/(W)* Error Signal Status [Setting condition] When the low level of the error signal is sampled [Clearing condition] When 0 is written to ERS after reading ERS = 1 3 PER 0 R/(W)* Parity Error [Setting conditi
PAGE 729
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEND 1 R Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR.
PAGE 730
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects Smart Card interface mode and its format. Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 3 SDIR These bits are always read as 1. 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits.
PAGE 731
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
PAGE 732
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in a 1-bit transfer interval) can be selected. For details, refer to section 15.7.
PAGE 733
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 3.6864 4 4.9152 5 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.
PAGE 734
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ (MHz) 9.8304 10 12 12.288 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.
PAGE 735
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4) Operating Frequency φ (MHz) 18 19.6608 20 25 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 79 –0.12 3 86 0.31 3 88 –0.25 3 110 –0.02 150 2 233 0.16 2 255 0.00 3 64 0.16 3 80 –0.47 300 2 116 0.16 2 127 0.00 2 129 0.16 2 162 0.15 600 1 233 0.16 1 255 0.00 2 64 0.16 2 80 –0.
PAGE 736
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Maximum Bit Rate (bit/s) n N 2 62500 0 0 10 312500 0 0 2.097152 65536 0 0 12 375000 0 0 2.4576 76800 0 0 12.288 384000 0 0 3 93750 0 0 14 437500 0 0 3.6864 115200 0 0 14.7456 460800 0 0 4 125000 0 0 16 500000 0 0 4.9152 153600 0 0 17.
PAGE 737
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) n 2 4 N n N 8 10 16 n N n N n N 20 n N 25 n N 110 3 70 — — 250 2 124 2 249 3 124 — — 3 249 500 1 249 2 124 2 249 — — 3 124 — — 1k 1 124 1 249 2 124 — — 2 249 — — 3 97 2.
PAGE 738
Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) Bit Rate (bit/s) n 30 N 33 n N 110 250 500 3 233 1k 3 116 3 128 2.5 k 2 187 2 205 5k 2 93 2 102 10 k 1 187 1 205 25 k 1 74 1 82 50 k 0 149 0 164 100 k 0 74 0 82 250 k 0 29 0 32 500 k 0 14 — — 1M — — — — 2.5 M 0 2 — — 5M — — — — Legend: Blank: Cannot be set. —: Can be set, but there will be a degree of error. *: Continuous transfer is not possible. Table 15.
PAGE 739
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) Operating Frequency φ (MHz) 7.1424 10.00 10.7136 13.00 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 1 1 0.00 0 1 30 0 1 25 0 1 8.99 Operating Frequency φ (MHz) 14.2848 16.00 18.00 20.
PAGE 740
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.10 IrDA Control Register (IrCR) IrCR selects the function of SCI_0. Bit Bit Name Initial Value R/W Description 7 IrE 0 R/W IrDA Enable Specifies normal SCI mode or IrDA mode for SCI_0 input/output.
PAGE 741
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.11 Serial Extension Mode Register (SEMR) SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by selecting the average transfer rate. SEMR is supported only in SCI_2 of the H8S/2678R Group. Bit Bit Name Initial Value R/W Description 7 to 4 — Undefined — Reserved 3 ABCS If these bits are read, an undefined value will be returned and cannot be modified.
PAGE 742
Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 1 0 ACS2 ACS1 ACS0 0 0 0 R/W R/W R/W Asynchronous clock source selection (valid when CKS1 = 1 in asynchronous mode) Selects the clock source for the average transfer rate. The basic clock can be automatically set by selecting the average transfer rate in spite of the value of ABCS. 000: External clock input 001: Selects 115.152 kbps which is the average transfer rate dedicated for φ = 10.667 MHz.
PAGE 743
Section 15 Serial Communication Interface (SCI, IrDA) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
PAGE 744
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
PAGE 745
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched at the middle of each bit by sampling the data at the rising edge of the 8th pulse of the basic clock as shown in figure 15.3.
PAGE 746
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin.
PAGE 747
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1.
PAGE 748
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.5 Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
PAGE 749
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
PAGE 750
Section 15 Serial Communication Interface (SCI, IrDA) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
PAGE 751
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception. Table 15.
PAGE 752
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
PAGE 753
Section 15 Serial Communication Interface (SCI, IrDA) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 15.9 Sample Serial Reception Data Flowchart (2) Rev. 3.
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Section 15 Serial Communication Interface (SCI, IrDA) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
PAGE 755
Section 15 Serial Communication Interface (SCI, IrDA) Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'AA H'01 (MPB= 1) ID transmission cycle = receiving station specification (MPB= 0) Data transmission cycle = data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.
PAGE 756
Section 15 Serial Communication Interface (SCI, IrDA) [1] [1] SCI initialization: Initialization Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1? Yes No Break output? The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled.
PAGE 757
Section 15 Serial Communication Interface (SCI, IrDA) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.
PAGE 758
Section 15 Serial Communication Interface (SCI, IrDA) 1 Start bit 0 Data (ID1) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data1) MPB D0 D1 D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 RXI interrupt request (multiprocessor interrupt) generated MPIE = 0 RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine If not this station’s ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not
PAGE 759
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1. Start of reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ∨ ORER = 1? [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
PAGE 760
Section 15 Serial Communication Interface (SCI, IrDA) [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.
PAGE 761
Section 15 Serial Communication Interface (SCI, IrDA) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character of communication data consists of 8-bit data. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
PAGE 762
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1.
PAGE 763
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
PAGE 764
Section 15 Serial Communication Interface (SCI, IrDA) Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev. 3.
PAGE 765
Section 15 Serial Communication Interface (SCI, IrDA) [1] Initialization Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes Read TEND flag in SSR [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin.
PAGE 766
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2.
PAGE 767
Section 15 Serial Communication Interface (SCI, IrDA) [1] Initialization Start of reception [2] Read ORER flag in SSR Yes [3] ORER = 1? No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
PAGE 768
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI is initialized.
PAGE 769
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Start of transmission/reception Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
PAGE 770
Section 15 Serial Communication Interface (SCI, IrDA) 15.7 Operation in Smart Card Interface Mode The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 15.7.1 Pin Connection Example Figure 15.21 shows an example of connection with the Smart Card.
PAGE 771
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.2 Data Format (Except for Block Transfer Mode) Figure 15.22 shows the transfer data format in Smart Card interface mode. • One frame consists of 8-bit data plus a parity bit in asynchronous mode. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame.
PAGE 772
Section 15 Serial Communication Interface (SCI, IrDA) As in the above sample start character, with the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode.
PAGE 773
Section 15 Serial Communication Interface (SCI, IrDA) falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula. M = (0.5 – 1 D – 0.5 ) – (L – 0.
PAGE 774
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR. Set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR.
PAGE 775
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.6 Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 15.26 illustrates the retransfer operation when the SCI is in transmit mode. 1.
PAGE 776
Section 15 Serial Communication Interface (SCI, IrDA) nth transfer frame Transfer frame n+1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR from TDR TEND [7] [9] FER/ERS [6] [8] Figure 15.26 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag generation timing is shown in figure 15.
PAGE 777
Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 15.28 Example of Transmission Processing Flow Rev. 3.
PAGE 778
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 15.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1.
PAGE 779
Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start reception ORER = 0 and PER = 0 No Yes Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 15.30 Example of Reception Processing Flow 15.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.
PAGE 780
Section 15 Serial Communication Interface (SCI, IrDA) CKE0 SCK Specified pulse width Specified pulse width Figure 15.31 Timing for Fixing Clock Output Level When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty cycle. Powering On: To secure the clock duty cycle from power-on, the following switching procedure should be followed. 1.
PAGE 781
Section 15 Serial Communication Interface (SCI, IrDA) When returning to smart card interface mode from software standby mode: 1. Exit the software standby state. 2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty cycle. Software standby Normal operation [1] [2] [3] [4] [5] Normal operation [6] [7] Figure 15.32 Clock Halt and Restart Procedure 15.
PAGE 782
Section 15 Serial Communication Interface (SCI, IrDA) IrDA TxD0/IrTxD Pulse encoder RxD0/IrRxD Pulse decoder SCI0 TxD RxD IrCR Figure 15.33 Block Diagram of IrDA Transmission: In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the IrDA interface (see figure 15.34). When the serial data is 0, a high pulse of 3/16 the bit rate (interval equivalent to the width of one bit) is output (initial value).
PAGE 783
Section 15 Serial Communication Interface (SCI, IrDA) UART frame Stop bit Data Start bit 0 1 0 1 0 0 1 Transmit 1 0 1 Receive IR frame Data Start bit 0 Bit cycle 1 0 1 0 Stop bit 0 1 1 0 1 Pulse width 1.6 µs to 3/16 bit cycle Figure 15.34 IrDA Transmit/Receive Operations Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the SCI.
PAGE 784
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.12 Settings of Bits IrCKS2 to IrCKS0 Bit Rate (bps) (Above) /Bit Period × 3/16 (µs) (Below) Operating Frequency φ (MHz) 2400 9600 19200 38400 57600 115200 78.13 19.53 9.77 4.88 3.26 1.63 2 010 010 010 010 010 — 2.097152 010 010 010 010 010 — 2.4576 010 010 010 010 010 — 3 011 011 011 011 011 — 3.6864 011 011 011 011 011 011 4.
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Section 15 Serial Communication Interface (SCI, IrDA) 15.9 Interrupt Sources 15.9.1 Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
PAGE 786
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.13 SCI Interrupt Sources Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation Priority 0 ERI0 Receive Error ORER, FER, PER Not possible Not possible High RXI0 Receive Data Full RDRF Possible Possible TXI0 Transmit Data Empty TDRE Possible Possible TEI0 Transmission End TEND Not possible Not possible 1 2 15.9.
PAGE 787
Section 15 Serial Communication Interface (SCI, IrDA) In Smart Card interface mode, as in normal serial communication interface mode, transfer can be carried out using the DTC or DMAC. In transmit operations, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out.
PAGE 788
Section 15 Serial Communication Interface (SCI, IrDA) 15.10.3 Mark State and Break Sending When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1.
PAGE 789
Section 15 Serial Communication Interface (SCI, IrDA) SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4 clocks. Figure 15.35 Example of Synchronous Transmission Using DTC 15.10.7 Operation in Case of Mode Transition • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode or software standby mode transition. TSR, TDR, and SSR are reset.
PAGE 790
Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.39 shows a sample flowchart for mode transition during reception. All data transmitted? No [1] Yes Read TEND flag in SSR TEND = 1 No Yes TE = 0 [2] Transition to software standby mode [3] [1] Data being transmitted is interrupted.
PAGE 791
Section 15 Serial Communication Interface (SCI, IrDA) End of transmission Start of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Port Start Stop Port input/output Port SCI TxD output High output SCI TxD output Figure 15.
PAGE 792
Section 15 Serial Communication Interface (SCI, IrDA) Read RDRF flag in SSR RDRF = 1 No [1] [1] Receive data being received becomes invalid. [2] [2] Includes module stop mode. Yes Read receive data in RDR RE = 0 Transition to software standby mode Exit from software standby mode Change operating mode? No Yes Initialization RE = 1 Figure 15.39 Sample Flowchart for Mode Transition during Reception Rev. 3.
PAGE 793
Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to twelve analog input channels to be selected. The block diagram of A/D converter is shown in figure 16.1. 16.1 Features • 10-bit resolution • Twelve input channels • Conversion time: 6.
PAGE 794
Section 16 A/D Converter Module data bus Vref 10-bit D/A AVSS AN0 AN1 A D D R A A D D R B A D D R C A D D R D * A D D R E * A D D R F * A D D R G * A D D R H A D C S R A D C R + AN2 – Multiplexer AN3 AN4 AN5 AN6 AN7 Bus interface Successive approximations register AVCC Internal data bus Comparator Control circuit Sample-andhold circuit AN12 AN13 AN14 AN15 ADI interrupt signal ADTRG Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: Conversion start trigger from 8-bit timer or TPU A/D
PAGE 795
Section 16 A/D Converter 16.2 Input/Output Pins Table 16.1 shows the pin configuration of the A/D converter. The twelve analog input pins are divided into two channel sets: channel set 0 (AN0 to AN7) and channel set 1 (AN12 to AN15). In the H8S/2678 Group, each channel set is divided into four channels × two groups: group 0 in channel set 0 (AN0 to AN3), group 1 in channel set 0 (AN4 to AN7), and group1 in channel set 1 (AN12 to AN15).
PAGE 796
Section 16 A/D Converter 16.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D data register E (ADDRE) • A/D data register F (ADDRF) • A/D data register G (ADDRG) • A/D data register H (ADDRH) • A/D control/status register (ADCSR) • A/D control register (ADCR) 16.3.
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Section 16 A/D Converter Table 16.
PAGE 798
Section 16 A/D Converter 16.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. • H8S/2678 Group Bit Bit Name Initial Value R/W Description 7 ADF 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
PAGE 799
Section 16 A/D Converter Bit Bit Name Initial Value R/W Description 3 CKS 0 R/W Clock Select Used together with the CKS1 bit in ADCR to set the A/D conversion time. When CKS1 = 0 0: 530 states (max) 1: 68 states (max) When CKS = 1 0: 266 states (max) 1: 134 states (max) 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W 0 CH0 0 R/W These bits are used together with the SCAN bit in ADCSR and the CH3 bit in ADCR to select the analog input channels.
PAGE 800
Section 16 A/D Converter • H8S/2678R Group Bit 7 Bit Name ADF Initial Value R/W Description 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
PAGE 801
Section 16 A/D Converter Bit Bit Name Initial Value R/W Description 3 CH3 0 R/W Channel select 3 to 0 2 CH2 0 R/W 1 CH1 0 R/W Selects analog input together with bits SCANE and SCANS in ADCR.
PAGE 802
Section 16 A/D Converter 16.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion start by an external trigger input. • H8S/2678 Group Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 6 TRGS0 0 R/W These bits select enabling or disabling of the start of A/D conversion by a trigger signal.
PAGE 803
Section 16 A/D Converter • H8S/2678R Group Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 6 TRGS0 0 R/W These bits select enabling or disabling of the start of A/D conversion by a trigger signal.
PAGE 804
Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D conversion. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 16.4.
PAGE 805
Section 16 A/D Converter 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the corresponding A/D data register to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first channel in the group starts again. 4.
PAGE 806
Section 16 A/D Converter (1) φ Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1) : ADCSR write cycle (2) : ADCSR address tD : A/D conversion start delay time tSPL : Input sampling time tCONV : A/D conversion time Figure 16.2 A/D Conversion Timing Table 16.
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Section 16 A/D Converter • H8S/2678R Group CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion start delay time tD 18 — 33 10 — 17 6 — 9 4 — 5 Input sampling time tSPL — 127 — — 63 — — 31 — — 15 — A/D conversion time tCONV 515 — 266 131 — 134 67 — 68 530 259 — Note: Values in the table are the number of states. Table 16.
PAGE 808
Section 16 A/D Converter 16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3 shows the timing.
PAGE 809
Section 16 A/D Converter 16.6 A/D Conversion Accuracy Definitions This LSI’s A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4).
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Section 16 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 16.4 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 16.5 A/D Conversion Accuracy Definitions Rev. 3.
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Section 16 A/D Converter 16.7 Usage Notes 16.7.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 16.7.
PAGE 812
Section 16 A/D Converter 16.7.3 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. 16.7.
PAGE 813
Section 16 A/D Converter 16.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7 and AN12 to AN15) should be connected between AVcc and AVss as shown in figure 16.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN7 and AN12 to AN15 must be connected to AVss.
PAGE 814
Section 16 A/D Converter Table 16.6 Analog Pin Specifications Item Min Max Unit Analog input capacitance — 20 pF Permissible signal source impedance — 10 kΩ 10 kΩ AN0 to AN7, AN12 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 16.8 Analog Input Pin Equivalent Circuit Rev. 3.
PAGE 815
Section 17 D/A Converter Section 17 D/A Converter 17.1 Features D/A converter features are listed below. • 8-bit resolution • Four output channels • Maximum conversion time of 10 µs (with 20-pF load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode • Setting the module stop mode DAC0001A_000020020400 Rev. 3.
PAGE 816
Bus interface Section 17 D/A Converter Module data bus Vref DACR23 DACR01 DA1 DADR3 8-bit D/A DADR2 DA2 DADR1 DA3 DADR0 AVCC DA0 AVSS Control circuit Legend: DADR0: DADR1: DADR2: DADR3: DACR01: DACR23: D/A data register 0 D/A data register 1 D/A data register 2 D/A data register 3 D/A control register 01 D/A control register 23 Figure 17.1 Block Diagram of D/A Converter Rev. 3.
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Section 17 D/A Converter 17.2 Input/Output Pins Table 17.1 shows the pin configuration of the D/A converter. Table 17.
PAGE 818
Section 17 D/A Converter 17.3.2 D/A Control Registers 01 and 23 (DACR01, DACR23) DACR01 and DACR23 control the operation of the D/A converter. DACR01 Bit Bit Name Initial Value R/W Description 7 DAOE1 0 R/W D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output (DA1) is disabled 1: Channel 1 D/A conversion is enabled; analog output (DA1) is enabled 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output.
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Section 17 D/A Converter Table 17.2 Control of D/A Conversion Bit 5 DAE Bit 7 DAOE1 Bit 6 DAOE0 Description 0 0 0 D/A conversion disabled 1 Channel 0 D/A conversion enabled, channel1 D/A conversion disabled 0 Channel 1 D/A conversion enabled, channel0 D/A conversion disabled 1 Channel 0 and 1 D/A conversions enabled 0 D/A conversion disabled 1 Channel 0 and 1 D/A conversions enabled 1 1 0 1 0 1 Rev. 3.
PAGE 820
Section 17 D/A Converter DACR23 Bit Bit Name Initial Value R/W Description 7 DAOE3 0 R/W D/A Output Enable 3 Controls D/A conversion and analog output. 0: Analog output (DA3) is disabled 1: Channel 3 D/A conversion is enabled; analog output (DA3) is enabled 6 DAOE2 0 R/W D/A Output Enable 2 Controls D/A conversion and analog output.
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Section 17 D/A Converter Table 17.3 Control of D/A Conversion Bit 5 DAE Bit 7 DAOE3 Bit 6 DAOE2 Description 0 0 0 D/A conversion disabled 1 Channel 2 D/A conversion enabled, channel3 D/A conversion disabled 0 Channel 3 D/A conversion enabled, channel2 D/A conversion disabled 1 Channel 2 and 3 D/A conversions enabled 0 D/A conversion disabled 1 Channel 2 and 3 D/A conversions enabled 1 1 0 1 0 1 17.
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Section 17 D/A Converter DADR0 write cycle DADR0 write cycle DACR01 write cycle DACR01 write cycle φ Address DADR0 Conversion data 1 Conversion data 2 DAOE0 DA0 Conversion result 2 Conversion result 1 High-impedance state tDCONV tDCONV Legend: tDCONV: D/A conversion time Figure 17.2 Example of D/A Converter Operation 17.5 Usage Notes 17.5.
PAGE 823
Section 18 RAM Section 18 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR).
PAGE 824
Section 18 RAM Rev. 3.
PAGE 825
Section 19 Flash Memory (F-ZTAT Version) Section 19 Flash Memory (F-ZTAT Version) The features of the flash memory included in the flash memory version are summarized below. The block diagram of the flash memory is shown in figure 19.1. 19.
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Section 19 Flash Memory (F-ZTAT Version) • Programming/erasing protection There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase operations.
PAGE 827
Section 19 Flash Memory (F-ZTAT Version) The differences between boot mode and user program mode are shown in table 19.1. Figure 19.3 shows boot mode. Figure 19.4 shows user program mode. Note: * Only in the H8S/2678 Group.
PAGE 828
Section 19 Flash Memory (F-ZTAT Version) 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication.
PAGE 829
Section 19 Flash Memory (F-ZTAT Version) 1. Initial state (1) The FWE assessment program that confirms that user program mode is entered, and (2) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. 2.
PAGE 830
Section 19 Flash Memory (F-ZTAT Version) 19.3 Block Configuration Figure 19.5 shows the block configuration of 384-kbyte flash memory and figure 19.6 shows that of 256-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 384-kbyte flash memory is divided into 64 kbytes (5 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks).
PAGE 831
Section 19 Flash Memory (F-ZTAT Version) EB0 Erase unit 4 kbytes H'000000 H'000001 H'000002 Programming unit: 128 bytes EB1 Erase unit 4 kbytes H'001000 H'001001 H'001002 Programming unit: 128 bytes EB2 Erase unit 4 kbytes H'002000 H'002001 H'002002 Programming unit: 128 bytes EB3 Erase unit 4 kbytes H'003000 H'003001 H'003002 Programming unit: 128 bytes EB4 Erase unit 4 kbytes H'004000 H'004001 H'004002 Programming unit: 128 bytes H'00407F EB7 Erase unit 4 kbytes H'007000 H'007
PAGE 832
Section 19 Flash Memory (F-ZTAT Version) EB0 Erase unit 4 kbytes H'000000 H'000001 H'000002 Programming unit: 128 bytes EB1 Erase unit 4 kbytes H'001000 H'001001 H'001002 Programming unit: 128 bytes EB2 Erase unit 4 kbytes H'002000 H'002001 H'002002 Programming unit: 128 bytes EB3 Erase unit 4 kbytes H'003000 H'003001 H'003002 Programming unit: 128 bytes EB4 Erase unit 4 kbytes H'004000 H'004001 H'004002 Programming unit: 128 bytes H'00407F EB7 Erase unit 4 kbytes H'007000 H'007
PAGE 833
Section 19 Flash Memory (F-ZTAT Version) 19.4 Input/Output Pins Table 19.2 shows the pin configuration of the flash memory. Table 19.
PAGE 834
Section 19 Flash Memory (F-ZTAT Version) Bit Bit Name Initial Value R/W Description 7 FWE 0/1 R Flash Write Enable Reflects the input level at the FWE pin. It is set to 1 when a high level is input to the FWE pin, and cleared to 0 when a low level is input. When this bit is cleared to 0, the flash memory transits to the hardware protection state. Note: In the H8S/2678R Group, this bit is reserved. This bit is always read as 0 in modes 1 and 2. This bit is always read as 1 in modes 3 to 7.
PAGE 835
Section 19 Flash Memory (F-ZTAT Version) Bit Bit Name Initial Value R/W Description 1 E 0 R/W Erase When this bit is set to 1 while FWE = 1*, SWE = 1, and ESU = 1, the flash memory transits to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while FWE = 1*, SWE = 1, and PSU = 1, the flash memory transits to program mode. When it is cleared to 0, program mode is cancelled. Note: * 19.5.2 Only in H8S/2678 Group.
PAGE 836
Section 19 Flash Memory (F-ZTAT Version) 19.5.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Set only one bit in EBR1 and EBR2 together (do not set more than one bit at the same time). Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0. For details, see table 19.3, Erase Blocks.
PAGE 837
Section 19 Flash Memory (F-ZTAT Version) 19.5.4 Erase Block Register 2 (EBR2) EBR2 specifies the flash memory erase area block. EBR2 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Set only one bit in EBR2 and EBR1 together (do not set more than one bit at the same time). Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0. For details, see table 19.3, Erase Blocks.
PAGE 838
Section 19 Flash Memory (F-ZTAT Version) Table 19.
PAGE 839
Section 19 Flash Memory (F-ZTAT Version) Bit Bit Name Initial Value R/W 7, 5 — All 0 R Description Reserved These bits always read as 0. 4 — 0 R/W Reserved The initial value should not be changed. 3 RAMS 0 R/W RAM Select Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, the flash memory is overlapped with part of RAM, and all flash memory block are in the program/eraseprotect state. When this bit is cleared to 0, the RAM emulation function is invalid.
PAGE 840
Section 19 Flash Memory (F-ZTAT Version) 19.6 On-Board Programming Modes In an on-board programming mode, programming, erasing, and verification for the on-chip flash memory can be performed. There are two on-board programming modes: boot mode and user program mode. Table 19.4 shows how to select boot mode. User program mode can be selected by setting the control bits by software. For a diagram that shows mode transitions of flash memory, see figure 19.2. Table 19.
PAGE 841
Section 19 Flash Memory (F-ZTAT Version) 19.6.1 Boot Mode When this LSI enters boot mode, the embedded boot program is started. The boot program transfers the programming control program from the externally connected host to the on-chip RAM via the SCI_1. When the flash memory is all erased, the programming control program is executed. Table 19.5 shows the boot mode operations between reset end and branching to the programming control program. 1.
PAGE 842
Section 19 Flash Memory (F-ZTAT Version) return when a program that is to be initiated in user program mode was accidentally erased and could not be executed in user program mode. Notes: 1. In boot mode, a part of the on-chip RAM area (H'FF8000 to H'FF87FF) is used by the boot program. Addresses H'FF8800 to H'FFBFFF is the area to which the programming control program is transferred from the host.
PAGE 843
Section 19 Flash Memory (F-ZTAT Version) Host Operation Communication Contents Processing Contents Bit rate adjustment Boot mode initiation Item Table 19.5 Boot Mode Operation LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 . . . H'00 • Measures low-level period of receive data H'00.
PAGE 844
Section 19 Flash Memory (F-ZTAT Version) Table 19.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 8 to 25 MHz 9,600 bps 8 to 25 MHz 19.6.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase program.
PAGE 845
Section 19 Flash Memory (F-ZTAT Version) Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM FWE = high* Execute user program/erase control program (flash memory programming) Clear FWE* Branch to flash memory application program Note: * Not available in H8S/2678R Group. Figure 19.7 Programming/Erasing Flowchart Example in User Program Mode 19.
PAGE 846
Section 19 Flash Memory (F-ZTAT Version) 3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 19.
PAGE 847
Section 19 Flash Memory (F-ZTAT Version) 3. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFA000 H'FFAFFF Flash memory EB8 to EB13 On-chip RAM H'FFBFFF H'5FFFF 384-kbyte flash memory Figure 19.9 Example of RAM Overlap Operation 19.
PAGE 848
Section 19 Flash Memory (F-ZTAT Version) 19.8.1 Program/Program-Verify When programming data or programs to the flash memory, the program/program-verify flowchart shown in figure 19.10 should be followed. Performing programming operations according to this flowchart will enable data or programs to be programmed to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address.
PAGE 849
Section 19 Flash Memory (F-ZTAT Version) Write pulse application subroutine Start of programming Write pulse application Start Enable WDT Set SWE bit in FLMCR1 Set PSU bit in FLMCR1 Wait (y) µs *6 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
PAGE 850
Section 19 Flash Memory (F-ZTAT Version) 19.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.11 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
PAGE 851
Section 19 Flash Memory (F-ZTAT Version) Start *1 Set SWE bit in FLMCR1 Wait (x) µs *2 n=1 *4 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (y) µs *2 Start of erase Set E bit in FLMCR1 Wait (z) ms *2 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) µs *2 Clear ESU bit in FLMCR1 Wait (β) µs *2 Disable WDT Set EV bit in FLMCR1 *2 Wait (γ) µs Set block start address to verify address H'FF dummy write to verify address Increment address Wait (ε) µs *2 Read verify data *3 Verify da
PAGE 852
Section 19 Flash Memory (F-ZTAT Version) 19.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or standby mode.
PAGE 853
Section 19 Flash Memory (F-ZTAT Version) The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is forcibly aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. The error protection state can be canceled by a power-on reset or in hardware standby mode. 19.
PAGE 854
Section 19 Flash Memory (F-ZTAT Version) 19.12 Usage Notes Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. 1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A).
PAGE 855
Section 19 Flash Memory (F-ZTAT Version) 5. Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when programming or erasing flash memory. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 6. Use the recommended algorithm when programming and erasing flash memory.
PAGE 856
Section 19 Flash Memory (F-ZTAT Version) Wait time: x Programming/ erasing Wait time: 100 µs possible φ Min 0 µs tOSC1 VCC tMDS*3 FWE Min 0 µs MD2 to MD0*1 tMDS*3 RES SWE set SWE cleared SWE bit (1) Boot Mode Wait time: x Programming/ erasing possible Wait time: 100 µs φ Min 0 µs tOSC1 VCC FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE cleared SWE bit (2) User Program Mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory
PAGE 857
Section 19 Flash Memory (F-ZTAT Version) Wait time: x Programming/ erasing possible Wait time: 100 µs φ Min 0 µs tOSC1 VCC MD2 to MD0*1 tMDS*3 RES SWE set SWE cleared SWE bit (1) Boot Mode Wait time: x Programming/ erasing possible Wait time: 100 µs φ Min 0 µs tOSC1 VCC MD2 to MD0*1 tMDS*3 RES SWE set SWE cleared SWE bit (2) User Program Mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution
PAGE 858
Section 19 Flash Memory (F-ZTAT Version) Wait time: x Programming/erasing possible Wait time: x Wait time: x Programming/erasing Programming/erasing possible possible Wait time: x Programming/erasing possible φ tOSC1 VCC Min 0 µs FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE set SWE bit SWE cleared Mode change*1 Boot mode Mode User change*1 mode User program mode User mode User program mode (1) H8S/2678 Group Wait time: x Wait time: x Programming/erasing Programming/erasing possible possible
PAGE 859
Section 19 Flash Memory (F-ZTAT Version) 19.13 Note on Switching from F-ZTAT Version to Masked ROM Version Care is required if application software developed on the F-ZTAT version is used when the FZTAT version is switched to the masked ROM version product. If an address in which a register for the F-ZTAT version is present is read (see section 23.1, Register Addresses (by functional module, in order of the corresponding section numbers)) in the masked ROM version, an undefined value will be returned.
PAGE 860
Section 19 Flash Memory (F-ZTAT Version) Rev. 3.
PAGE 861
Section 20 Masked ROM Section 20 Masked ROM This Group microcomputer has 64, 128, or 256 kbytes of on-chip masked ROM. The on-chip ROM is connected to the CPU, data transfer controller (DTC), and DMA controller (DMAC) with a 16-bit data bus. The on-chip ROM can be accessed by the CPU, DTC, and DMAC in 8 or 16-bit units. The data in the on-chip ROM can always be accessed in one state.
PAGE 862
Section 20 Masked ROM Internal data bus (upper 8 bits) Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Internal data bus (lower 8 bits) H'000000 H'000001 H'100000 H'100001 H'000002 H'000003 H'100002 H'100003 H'00FFFE H'00FFFF H'10FFFE H'10FFFF Modes 4 and 7 Modes 5 and 6 Figure 20.3 Block Diagram of 64-kbyte Masked ROM (HD6432673) The operating mode enables or disables the on-chip ROM.
PAGE 863
Section 21 Clock Pulse Generator Section 21 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and internal clocks. The clock pulse generator consists of an oscillator circuit, PLL circuit, and divider. Figure 21.1 shows a block diagram of the clock pulse generator.
PAGE 864
Section 21 Clock Pulse Generator 21.1.1 System Clock Control Register (SCKCR) SCKCR controls φ clock output and selects operation when the frequency multiplication factor used by the PLL circuit is changed, and the division ratio used by the divider. Bit Bit Name Initial Value R/W Description 7 PSTOP 0 R/W φ Clock Output Disable Controls φ output.
PAGE 865
Section 21 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 2 1 0 SCK2 SCK1 SCK0 0 0 0 R/W R/W R/W System Clock Select 2 to 0 Select the division ratio. 000: 1/1 001: 1/2 010: 1/4 011: 1/8 100: 1/16 101: 1/32 11X: Setting prohibited Legend: 21.1.2 X: Don’t care PLL Control Register (PLLCR) PLLCR sets the frequency multiplication factor used by the PLL circuit.
PAGE 866
Section 21 Clock Pulse Generator 21.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 21.2.1 Connecting a Crystal Resonator A crystal resonator can be connected as shown in the example in figure 21.2. Select the damping resistance Rd according to table 20.1. An AT-cut parallel-resonance type should be used. Figure 21.3 shows the equivalent circuit of the crystal resonator.
PAGE 867
Section 21 Clock Pulse Generator Table 21.2 Crystal Resonator Characteristics Frequency (MHz) 8 12 16 20 25 RS max (Ω) 80 60 50 40 40 C0 max (pF) 7 7 7 7 7 21.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 21.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode. Table 21.
PAGE 868
Section 21 Clock Pulse Generator Table 21.3 External Clock Input Conditions VCC = 3.0 V to 3.6 V Item Symbol Min Max Unit Test Conditions External clock input low pulse width tEXL 15 — ns Figure 21.5 External clock input high pulse width tEXH 15 — ns External clock rise time tEXr — 5 ns External clock fall time tEXf — 5 ns Clock low pulse width tCL 0.4 0.6 tcyc Clock high pulse width tCH 0.4 0.6 tcyc tEXH tEXL EXTAL VCC × 0.5 tEXr tEXf Figure 21.
PAGE 869
Section 21 Clock Pulse Generator 2. A value is set in bits STS3 to STS0 to give the specified transition time. 3. The target value is set in bits STC1 and STC0, and a transition is made to software standby mode. 4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. 5. Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS3 to STS0. 6.
PAGE 870
Section 21 Clock Pulse Generator consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 21.5.3 Notes on Board Design When using the crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillation circuit to prevent induction from interfering with correct oscillation. See figure 21.6.
PAGE 871
Section 22 Power-Down Modes Section 22 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on.
PAGE 872
Section 22 Power-Down Modes Table 22.
PAGE 873
Section 22 Power-Down Modes STBY pin = low Reset state STBY pin = high RES pin = low Hardware standby mode RES pin = high SSBY = 0 SLEEP instruction High-speel mode (Internal clock is PLL circuit output clock) SCK2 to SCK0 = 0 SCK2 to SCK0 ≠ 0 Clock division mode Sleep mode Any interrupt SLEEP instruction Interrupt*1 All module-clocks-stop mode SLEEP instruction SSBY = 1 Software standby mode External interrupt*2 Program execution state : Transition after exception handling MSTPCR = H'FFFF (H'
PAGE 874
Section 22 Power-Down Modes 22.1 Register Descriptions The registers relating to the power-down mode are shown below. For details on the system clock control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR). • System clock control register (SCKCR) • Standby control register (SBYCR) • Module stop control register H (MSTPCRH) • Module stop control register L (MSTPCRL) 22.1.1 Standby Control Register (SBYCR) SBYCR performs software standby mode control.
PAGE 875
Section 22 Power-Down Modes Bit Bit Name Initial Value R/W Description 5, 4 — All 0 — Reserved These bits are always read as 0. The initial value should not be changed. 3 2 1 0 STS3 STS2 STS1 STS0 1 1 1 1 R/W R/W R/W R/W Standby Timer Select 3 to 0 These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 22.
PAGE 876
Section 22 Power-Down Modes 22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCR performs module stop mode control. Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0 clears the module stop mode.
PAGE 877
Section 22 Power-Down Modes MSTPCRL Bit Bit Name Initial Value R/W Module 7 MSTP7 1 R/W — 6 MSTP6 1 R/W A/D converter 5 MSTP5 1 R/W — 4 MSTP4 1 R/W — 3 MSTP3 1 R/W Serial communication interface 2 (SCI_2) 2 MSTP2 1 R/W Serial communication interface 1 (SCI_1) 1 MSTP1 1 R/W Serial communication interface 0 (SCI_0) 0 MSTP0 1 R/W 8-bit timer (TMR) 22.2 Operation 22.2.
PAGE 878
Section 22 Power-Down Modes 22.2.2 Sleep Mode Transition to Sleep Mode: When the SLEEP instruction is executed when the SSBY bit is 0 in SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained. Other peripheral functions do not stop. Exiting Sleep Mode: Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
PAGE 879
Section 22 Power-Down Modes IRQ15 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. • Clearing with the RES Pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling.
PAGE 880
Section 22 Power-Down Modes Table 22.2 Oscillation Stabilization Time Settings φ* [MHz] Standby STS3 STS2 STS1 STS0 Time 33 25 20 13 10 8 Unit 0 µs 0 0 1 1 0 1 1 0 0 1 1 0 1 0 Reserved — — — — — — 1 Reserved — — — — — — 0 Reserved — — — — — — 1 Reserved — — — — — — 0 Reserved — — — — — — 1 64 1.9 2.6 3.2 4.9 6.4 8.0 0 512 15.5 20.5 25.6 39.4 51.2 64.0 1 1024 31.0 41.0 51.2 78.8 102.4 128.0 0 2048 62.1 81.9 102.
PAGE 881
Section 22 Power-Down Modes Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG=1 SSBY=1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 NMI exception handling SLEEP instruction Figure 22.2 Software Standby Mode Application Example 22.2.4 Hardware Standby Mode Transition to Hardware Standby Mode: When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
PAGE 882
Section 22 Power-Down Modes subsequently driven high, a transition is made to the program execution state via the reset exception handling state. Hardware Standby Mode Timing: Figure 22.3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high.
PAGE 883
Section 22 Power-Down Modes 22.2.
PAGE 884
Section 22 Power-Down Modes 22.4 Usage Notes 22.4.1 I/O Port Status In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 22.4.2 Current Dissipation during Oscillation Stabilization Standby Period Current dissipation increases during the oscillation stabilization standby period. 22.4.
PAGE 885
Section 23 List of Registers Section 23 List of Registers This section gives information on the on-chip I/O registers and is configured as described below. 1. Register Addresses (by functional module, in order of the corresponding section numbers) • Descriptions by functional module, in order of the corresponding section numbers Entries that consist of  lines are for separation of the functional modules. • Access to reserved addresses which are not described in this list is prohibited.
PAGE 886
Section 23 List of Registers Register Name Abbreviation Bit No.
PAGE 887
Section 23 List of Registers Register Name Abbreviation Bit No.
PAGE 888
Section 23 List of Registers Register Name Abbreviation Bit No.
PAGE 889
Section 23 List of Registers Register Name Abbreviation Bit No.
PAGE 890
Section 23 List of Registers Register Name Abbreviation Bit No.
PAGE 891
Section 23 List of Registers Register Name Abbreviation Bit No.
PAGE 892
Section 23 List of Registers Register Name Abbreviation Bit No.
PAGE 893
Section 23 List of Registers Abbreviation Bit No.
PAGE 894
Section 23 List of Registers Register Name Abbreviation Bit No.
PAGE 895
Section 23 List of Registers Register Name Abbreviation Bit No.
PAGE 896
Section 23 List of Registers 23.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.
PAGE 897
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module EDSAR_2 — — — — — — — — EXDMAC_2 EDDAR_2 — — — — — — — — EDTCR_2 — — — — — — — — EDMDR_2 EDA BEF EDRAKE ETENDE EDREQS AMS MDS1 MDS0 EDACR_2 EDIE IRF TCEIE SDIR DTSIZE BGUP — — SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 EDSAR_3 — — — — — — — — EDDAR_3 — — — — — — — —
PAGE 898
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ITSR ITS15 ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 INT ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0 SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 SSIER ISCRH ISCRL IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB IRQ9SCA IRQ8SCB IRQ8SCA IRQ7SCB IRQ7SCA
PAGE 899
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_3 MD0 TMDR_3 — — BFB BFA MD3 MD2 MD1 TIORH_3 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA TSR_3 — — — TCFV TGFD TGFC TGFB TGFA TCNT_3 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRA_
PAGE 900
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TGRA_5 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 WTCRAH — W72 W71 W70 — W62 W61 W60 WTCRAL — W52 W51 W5
PAGE 901
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MAR_0BL Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 DMAC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IOAR_0B Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit8 ETCR_0B MAR_1AH MAR_1AL IOAR_1A ETCR_1A MAR_1BH MAR_1BL IOAR_1B ETCR_1B Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
PAGE 902
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTC*10 DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCERC — DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCERD DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCERE DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCERF DTCEF7 DTCEF6 DTCEF5 D
PAGE 903
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORT6 — — P65 P64 P63 P62 P61 P60 PORT PORT7 — — P75 P74 P73 P72 P71 P70 PORT8 — — P85 P84 P83 P82 P81 P80 PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTF PF7 PF6 PF5 PF4
PAGE 904
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SMR_1 C/A/ GM*2 CHR/ 3 BLK* PE O/E STOP/ BCP1*4 MP/ 5 BCP0* CKS1 CKS0 BRR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCI_1, Smart card interface 1 SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SSR_1 TDRE RDRF ORER FER/ 6 ERS* PER TEND MPB MPBT RDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCMR_1 — —
PAGE 905
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DADR0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 D/A DADR1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACR01 DAOE1 DAOE0 DAE — — — — — DADR2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DADR3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACR23 DAOE3 DAOE2 DAE — — — — — TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_0 TCR_1 CMIEB CMIEA
PAGE 906
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TGRB_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_0 TGRC_0 TGRD_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCR_1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
PAGE 907
Section 23 List of Registers 10. Loaded in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 11. For short address mode 12. For full address mode Rev. 3.
PAGE 908
Section 23 List of Registers 23.
PAGE 909
Section 23 List of Registers Register Abbreviation Reset HighSpeed Clock Division Sleep Module Stop All Module Clock Stop Software Hardware Standby Standby Module IPRG Initialized — — — — — — INT Initialized IPRH Initialized — — — — — — Initialized IPRI Initialized — — — — — — Initialized IPRJ Initialized — — — — — — Initialized IPRK Initialized — — — — — — Initialized ITSR Initialized — — — — — — Initialized SSIER Initialized — — — — —
PAGE 910
Section 23 List of Registers Register Abbreviation Reset HighSpeed Clock Division Sleep Module Stop All Module Clock Stop Software Hardware Standby Standby Module TCR_3 Initialized — — — — — — Initialized TPU_3 TMDR_3 Initialized — — — — — — Initialized TIORH_3 Initialized — — — — — — Initialized TIORL_3 Initialized — — — — — — Initialized TIER_3 Initialized — — — — — — Initialized TSR_3 Initialized — — — — — — Initialized TCNT_3 Initialized
PAGE 911
Section 23 List of Registers Register Abbreviation Reset HighSpeed Clock Division Sleep Module Stop All Module Clock Stop Software Hardware Standby Standby Module CSACRL Initialized — — — — — — Initialized BSC BROMCRH Initialized — — — — — — Initialized BROMCRL Initialized — — — — — — Initialized BCR Initialized — — — — — — Initialized RAMER* 2 Initialized — — — — — — Initialized FLASH DRAMCR Initialized — — — — — — Initialized BSC DRACCR I
PAGE 912
Section 23 List of Registers Register Abbreviation Reset HighSpeed Clock Division Sleep Module Stop All Module Clock Stop Software Hardware Standby Standby Module DTCERA Initialized — — — — — — Initialized DTC DTCERB Initialized — — — — — — Initialized DTCERC Initialized — — — — — — Initialized DTCERD Initialized — — — — — — Initialized DTCERE Initialized — — — — — — Initialized DTCERF Initialized — — — — — — Initialized DTCERG Initialized —
PAGE 913
Section 23 List of Registers Register Abbreviation Reset HighSpeed Clock Division Sleep Module Stop All Module Clock Stop Software Hardware Standby Standby Module PORT7 — — — — — — — — PORT PORT8 — — — — — — — — PORTA — — — — — — — — PORTB — — — — — — — — PORTC — — — — — — — — PORTD — — — — — — — — PORTE — — — — — — — — PORTF — — — — — — — — PORTG — — — — — — — — P1DR Initialized — — — — — Initialized — P2DR
PAGE 914
Section 23 List of Registers Register Abbreviation Reset HighSpeed Clock Division Sleep Module Stop SMR_1 Initialized — — — BRR_1 Initialized — — SCR_1 Initialized — — TDR_1 Initialized — SSR_1 Initialized RDR_1 Initialized SCMR_1 Initialized — — SMR_2 Initialized — — BRR_2 Initialized — — SCR_2 Initialized — TDR_2 Initialized — SSR_2 Initialized — All Module Clock Stop Software Hardware Standby Standby Module Initialized Initialized Initialized Initialized
PAGE 915
Section 23 List of Registers Register Abbreviation Reset HighSpeed Clock Division Sleep Module Stop All Module Clock Stop Software Hardware Standby Standby TCORA_0 Initialized — — — — — — Initialized TCORA_1 Initialized — — — — — — Initialized TCORB_0 Initialized — — — — — — Initialized TCORB_1 Initialized — — — — — — Initialized TCNT_0 Initialized — — — — — — Initialized TCNT_1 Initialized — — — — — — Initialized TCSR Initialized — — — — —
PAGE 916
Section 23 List of Registers Register Abbreviation Reset HighSpeed Clock Division Sleep Module Stop All Module Clock Stop Software Hardware Standby Standby Module TCR_2 Initialized — — — — — — Initialized TPU_2 TMDR_2 Initialized — — — — — — Initialized TIOR_2 Initialized — — — — — — Initialized TIER_2 Initialized — — — — — — Initialized TSR_2 Initialized — — — — — — Initialized TCNT_2 Initialized — — — — — — Initialized TGRA_2 Initialized —
PAGE 917
Section 24 Electrical Characteristics Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to + 4.6* V PLLVCC Input voltage (except port 4, P54 to P57) Vin –0.3 to VCC + 0.3 V Input voltage (port 4, P54 to P57) Vin –0.3 to AVCC + 0.3 V Reference power supply voltage Vref V Analog power supply voltage AVCC –0.3 to AVCC + 0.3 –0.
PAGE 918
Section 24 Electrical Characteristics 24.2 DC Characteristics Table 24.2 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, 1 VSS = AVSS = 0 V* , Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Min Typ Max Test Unit Conditions – VCC × 0.2 — — V + — — VCC × 0.7 V VCC × 0.07 — — V AVCC × 0.2 — — V — — AVCC × 0.
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Section 24 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions Output low voltage All output pins VOL — — 0.4 V IOL = 1.6 mA Input leakage current RES |Iin| — — 10.0 µA STBY, NMI, MD2 to MD0, 4 DCTL* — — 1.0 µA Vin = 0.5 to VCC – 0.5 V Port 4, P54 to P57 — — 1.0 µA Vin = 0.5 to AVCC – 0.5 V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
PAGE 920
Section 24 Electrical Characteristics Table 24.3 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, 1 VSS = AVSS = 0 V* , Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Three-state leakage current (off state) Ports 1 to 3, P50 to P53, ports 6 to 8, ports A to H Input pull-up Ports A to E MOS current Symbol Min Typ Max Test Unit Conditions | ITSI | — — 1.0 µA Vin = 0.5 to VCC – 0.
PAGE 921
Section 24 Electrical Characteristics 2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output pins unloaded and all input pull-up MOSs in the off state. 3. The values are for VRAM ≤ VCC < 3.0 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 1.0 (mA) + 1.2 (mA/(MHz × V)) × VCC × f (normal operation) ICCmax = 1.0 (mA) + 1.0 (mA/(MHz × V)) × VCC × f (sleep mode) 5. The values are for reference. Table 24.
PAGE 922
Section 24 Electrical Characteristics 24.3 AC Characteristics 3V RL C = 50 pF: ports A to H C = 30 pF: ports 1 to 3, P50 to P53, ports 6 to 8 LSI output pin C RH Figure 24.1 Output Load Circuit Rev. 3.00 Mar 17, 2006 page 870 of 926 REJ09B0283-0300 RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement level: 1.5 V (VCC = 2.7 V to 3.
PAGE 923
Section 24 Electrical Characteristics Clock Timing Table 24.5 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 30.3 500 ns Figure 24.2 Clock pulse high width tCH 10 — ns Figure 24.
PAGE 924
Section 24 Electrical Characteristics tcyc tCH tCf φ tCr tCL tcdif tsdcf tsdcr SDRAMφ tSDCH tSDCL Figure 24.3 SDRAMφ φ Timing* Note: Not supported in the H8S/2678 Group. EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 24.4 (1) Oscillation Stabilization Timing Rev. 3.
PAGE 925
Section 24 Electrical Characteristics Oscillator φ NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 SLEEP instruction Figure 24.4 (2) Oscillation Stabilization Timing Rev. 3.
PAGE 926
Section 24 Electrical Characteristics Control Signal Timing Table 24.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 — ns Figure 24.
PAGE 927
Section 24 Electrical Characteristics φ tNMIS tNMIH NMI tNMIW tIRQW IRQi (i = 0 to 15)* tIRQS tIRQH IRQ (edge input) tIRQS IRQ (level input) Note: * Necessary for SSIER setting to clear software standby mode. Figure 24.6 Interrupt Input Timing Rev. 3.
PAGE 928
Section 24 Electrical Characteristics Bus Timing Table 24.7 Bus Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Address delay time tAD — 20 ns Address setup time 1 tAS1 0.5 × tcyc – 13 — ns Figures 24.7 to 24.21 Address setup time 2 tAS2 1.
PAGE 929
Section 24 Electrical Characteristics Table 24.8 Bus Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions WR delay time 1 tWRD1 — 15 ns WR delay time 2 tWRD2 — 15 ns Figures 24.7 to 24.21 WR pulse width 1 tWSW1 1.0 × tcyc – 13 — ns WR pulse width 2 tWSW2 1.
PAGE 930
Section 24 Electrical Characteristics Item Symbol Min Max Unit Test Conditions Self-refresh precharge time 1 tRPS1 2.5 × tcyc – 20 — ns Self-refresh precharge time 2 tRPS2 3.0 × tcyc – 20 — ns Figures 24.22, 24.23 WAIT setup time tWTS 25 — ns Figure 24.15 WAIT hold time tWTH 5 — ns BREQ setup time tBREQS 30 — ns BACK delay time tBACD — 15 ns Bus floating time tBZD — 40 ns BREQO delay time tBRQOD — 25 ns Figure 24.25 Address delay time 2* tAD2 — 16.
PAGE 931
Section 24 Electrical Characteristics T1 T2 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC5 tAA2 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 tAA3 D15 to D0 tAS1 tWRD2 tWRD2 tAH1 HWR, LWR tWDD Write tWSW1 tWDH1 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK0 to EDACK3 Figure 24.7 Basic Bus Timing: Two-State Access Rev. 3.
PAGE 932
Section 24 Electrical Characteristics T1 T2 T3 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 tAA4 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tRDS2 tAC4 tRDH2 tAA5 D15 to D0 tAS2 tWRD1 HWR, LWR tWDS1 tWDD Write tAH1 tWRD2 tWSW2 tWDH1 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK0 to EDACK3 Figure 24.8 Basic Bus Timing: Three-State Access Rev. 3.
PAGE 933
Section 24 Electrical Characteristics T1 T2 Tw tWTS tWTH tWTS tWTH T3 φ A23 to A0 CS7 to CS0 AS RD Read (RDNn = 1) D15 to D0 RD Read (RDNn = 0) D15 to D0 HWR, LWR Write D15 to D0 WAIT Figure 24.9 Basic Bus Timing: Three-State Access, One Wait Rev. 3.
PAGE 934
Section 24 Electrical Characteristics Th T1 T2 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS3 tAH3 tRSD1 tRSD1 RD Read (RDNn = 1) tAC5 tRDS1 tRDH1 tRSD1 tRSD2 D15 to D0 tAS3 tAH2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 D15 to D0 tAS3 tAH3 tWRD2 tWRD2 HWR, LWR tWDD Write tWDS2 tWSW1 tWDH3 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK0 to EDACK3 Figure 24.10 Basic Bus Timing: Two-State Access (CS CS Assertion Period Extended) Rev. 3.
PAGE 935
Section 24 Electrical Characteristics Th T1 T2 T3 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS3 tRSD1 tAH3 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 D15 to D0 tAS3 tAH2 tRSD2 tRSD1 RD Read (RDNn = 0) tRDS2 tRDH2 tAC4 D15 to D0 tAS4 HWR, LWR tWDD Write tWRD2 tAH3 tWRD1 tWDS3 tWSW2 tWDH3 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK0 to EDACK3 Figure 24.11 Basic Bus Timing: Three-State Access (CS CS Assertion Period Extended) Rev. 3.
PAGE 936
Section 24 Electrical Characteristics T1 T2 T1 T1 φ A23 to A6, A0 tAD A5 to A1 CS7 to CS0 AS tRSD2 RD tAA1 tRDS2 tRDH2 Read D15 to D0 HWR, LWR Figure 24.12 Burst ROM Access Timing: One-State Burst Access Rev. 3.
PAGE 937
Section 24 Electrical Characteristics T1 T2 T3 T1 T2 φ A23 to A6, A0 tAD A5 to A1 CS7 to CS0 tAH1 tAS1 tASD AS tASD tRSD2 RD Read tAA3 tRDS2 tRDH2 D15 to D0 HWR, LWR Figure 24.13 Burst ROM Access Timing: Two-State Burst Access Rev. 3.
PAGE 938
Section 24 Electrical Characteristics Tr Tp Tc1 Tc2 φ tAD tAD A23 to A0 tAS3 RAS5 to RAS2 tCSD3 tAH1 tCSD2 tAS2 tPCH2 tAH2 tCASD1 tCASD1 UCAS tCASW1 LCAS tOED1 tOED1 tAC1 OE, RD Read HWR tAA3 tRDS2 tRDH2 tAC4 D15 to D0 OE, RD tWRD2 Write tWCS1 tWCH1 tWRD2 HWR tWDD tWDS1 tWDH2 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK0 to EDACK3 Notes: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Figure 24.
PAGE 939
Section 24 Electrical Characteristics Tp Tr Tc1 Tcw Tcwp Tc2 φ A23 to A0 RAS5 to RAS2 UCAS, LCAS OE, RD Read HWR D15 to D0 UCAS, LCAS OE, RD Write HWR D15 to D0 AS tWTS tWTH tWTS tWTH WAIT DACK0, DACK1 EDACK0 to EDACK3 Notes: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Tcw : Wait cycle inserted by programmable wait function Tcwp: Wait cycle inserted by pin wait function Figure 24.15 DRAM Access Timing: Two-State Access, One Wait Rev. 3.
PAGE 940
Section 24 Electrical Characteristics Tp Tr Tc2 Tc1 Tc1 Tc2 φ A23 to A0 RAS5 to RAS2 tCPW1 UCAS LCAS OE, RD Read HWR tAC3 D15 to D0 OE, RD Write tRCH HWR tRCS1 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK0 to EDACK3 Notes: DACK and EDACK timing: when DDS = 1 and EDDS = 1 RAS timing: when RAST = 0 Figure 24.16 DRAM Access Timing: Two-State Burst Access Rev. 3.
PAGE 941
Section 24 Electrical Characteristics Tp Tr Tc1 Tc2 Tc3 φ tAD tAD A23 to A0 tAS2 RAS5 to RAS2 tCSD3 tAH2 tCSD2 tPCH1 tAS3 tAH3 tCASD1 tCASD2 UCAS tCASW2 LCAS tOED2 tOED1 tAC2 OE, RD Read HWR tAA5 tRDS2 tRDH2 tAC7 D15 to D0 OE, RD Write tWCS2 tWRD2 tWCH2 tWRD2 HWR tWDD tWDS2 tWDH3 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK0 to EDACK3 Notes: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 1 Figure 24.
PAGE 942
Section 24 Electrical Characteristics Tp Tr Tc1 Tcw Tcwp Tc2 Tc3 φ A23 to A0 RAS5 to RAS2 UCAS, LCAS OE, RD Read HWR D15 to D0 UCAS, LCAS OE Write HWR D15 to D0 tWTS tWTH tWTS tWTH WAIT DACK0, DACK1 EDACK0, EDACK1 Notes: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Tcw : Tcwp: Wait cycle inserted by programmable wait function Wait cycle inserted by pin wait function Figure 24.18 DRAM Access Timing: Three-State Access, One Wait Rev. 3.
PAGE 943
Section 24 Electrical Characteristics Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ A23 to A0 RAS5 to RAS0 tCPW2 UCAS LCAS OE, RD Read HWR tAC8 D15 to D0 OE, RD Write tRCH HWR tRCS2 D15 to D0 AS DACK0, DACK1 EDACK0 to EDACK3 Notes: DACK and EDACK timing: when DDS = 1 and EDDS = 1 RAS timing: when RAST = 1 Figure 24.19 DRAM Access Timing: Three-State Burst Access Rev. 3.
PAGE 944
Section 24 Electrical Characteristics TRp TRr TRc1 TRc2 φ tCSD1 tCSD2 RAS5 to RAS2 tCSR1 tCASD1 tCASD1 UCAS, LCAS OE Figure 24.20 CAS-Before-RAS Refresh Timing TRp TRrw TRr TRc1 TRcw TRc2 φ tCSD1 tCSD2 RAS5 to RAS2 UCAS, LCAS tCSR2 tCASD1 OE Figure 24.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) Rev. 3.
PAGE 945
Section 24 Electrical Characteristics Self-refresh TRp TRr TRc TRc DRAM access Tpsr Tp Tr φ tCSD2 tCSD2 RAS5 to RAS2 tRPS2 tCASD1 tCASD1 UCAS, LCAS OE Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) Self-refresh TRp TRr TRc TRc Tpsr DRAM access Tp Tr φ tCSD2 RAS5 to RAS2 tCASD1 tCSD2 tRPS1 tCASD1 UCAS, LCAS OE Figure 24.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) Rev. 3.
PAGE 946
Section 24 Electrical Characteristics φ tBREQS tBREQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0 CS7 to CS0 (RAS5 to RAS2) D15 to D0 AS, RD HWR, LWR UCAS, LCAS, OE Figure 24.24 External Bus Release Timing φ BACK tBRQOD tBRQOD BREQO Figure 24.25 External Bus Request Output Timing Rev. 3.
PAGE 947
Section 24 Electrical Characteristics Tp Tr Tc1 Tw Tc2 φ SDRAMφ tAD2 Address bus Precharge-sel RAS tCSD4 tCSD4 tCSD4 CAS Read tCSD4 tCSD4 tCSD4 WE CKE tDQMD High tDQMD DQMU, DQML tRDS3 tRDH3 Data bus tCSD4 tCSD4 RAS tCSD4 CAS tCSD4 tCSD4 tCSD4 WE tCSD4 tCSD4 Write CKE High tDQMD DQMU, DQML tDQMD tWDD Data bus tWDH4 Figure 24.26 Synchronous DRAM Basic Access Timing (CAS Latency 2) Note: Not supported in the H8S/2678 Group. Rev. 3.
PAGE 948
Section 24 Electrical Characteristics TRp TRr Software standby TRr2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE tCKED CKE tCKED Figure 24.27 Synchronous DRAM Self-Refresh Timing Note: Not supported in the H8S/2678 Group. Rev. 3.
PAGE 949
Section 24 Electrical Characteristics Tp Tr Tc1 Tc2 TRr Ttp2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE tCKED tCKED CKE DQMU, DQML Data bus DACK or EDACK Figure 24.28 Read Data: Two-State Expansion (CAS Latency 2) Note: Not supported in the H8S/2678 Group. Rev. 3.
PAGE 950
Section 24 Electrical Characteristics DMAC and EXDMAC Timing Table 24.9 DMAC and EXDMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions DREQ setup time tDRQS 25 — ns Figure 24.32 DREQ hold time tDRQH 10 — TEND delay time tTED — 18 ns Figure 24.
PAGE 951
Section 24 Electrical Characteristics T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK0 to EDACK3 Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access Rev. 3.
PAGE 952
Section 24 Electrical Characteristics T1 T2 T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK0 to EDACK3 Figure 24.30 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access Rev. 3.
PAGE 953
Section 24 Electrical Characteristics T1 T2 or T3 φ tTED tTED tETED tETED TEND0, TEND1 ETEND0 to ETEND3 Figure 24.31 DMAC and EXDMAC TEND/ETEND TEND ETEND Output Timing φ tDRQS tDRQH DREQ0, DREQ1 tEDRQS tDERQH EDREQ0 to EDREQ3 Figure 24.32 DMAC and EXDMAC DREQ/EDREQ DREQ EDREQ Input Timing φ tEDRKD tEDRKD EDRAK0 to EDRAK3 Figure 24.33 EXDMAC EDRAK Output Timing Rev. 3.
PAGE 954
Section 24 Electrical Characteristics Timing of On-Chip Peripheral Modules Table 24.10 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
PAGE 955
Section 24 Electrical Characteristics T1 T2 φ tPRS tPRH Ports 1 to 8, A to H (read) tPWD Ports 1 to 3, 6 to 9, P53 to P50, ports A to H (write) Figure 24.34 I/O Port Input/Output Timing φ tPOD PO15 to PO0 Figure 24.35 PPG Output Timing φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 24.36 TPU Input/Output Timing Rev. 3.
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Section 24 Electrical Characteristics φ tTCKS tTCKS TCLKA to TCLKD tTCKWH tTCKWL Figure 24.37 TPU Clock Input Timing φ tTMOD TMO0, TMO1 Figure 24.38 8-Bit Timer Output Timing φ tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 24.39 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 Figure 24.40 8-Bit Timer Reset Input Timing Rev. 3.
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Section 24 Electrical Characteristics φ tWOVD tWOVD WDTOVF Figure 24.41 WDT Output Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 24.42 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 24.43 SCI Input/Output Timing: Synchronous Mode φ tTRGS ADTRG Figure 24.44 A/D Converter External Trigger Input Timing Rev. 3.
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Section 24 Electrical Characteristics 24.4 A/D Conversion Characteristics Table 24.11 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Min Typ Max Unit Resolution 10 10 10 Bit Conversion time — — 8.
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Section 24 Electrical Characteristics 24.6 Flash Memory Characteristics Table 24.13 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
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Section 24 Electrical Characteristics Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time N tP (max) = ∑ wait time after P bit setting (z) i=1 5.
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Appendix Appendix A.
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Appendix Port Name MCU Operating Mode*1 Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode P55, P54 1 to 7 T T T T Input port P53 to P50 1 to 7 T T Keep Keep I/O port Port 6 1 to 7 T T Keep Keep I/O port Port 7 1 to 7 T T Keep Keep I/O port Port 8 1 to 7 T T Keep Keep I/O port PA7/A23 1 to 7 T T [OPE = 0, address output] [Address output] [Address output] PA6/A22 T A23 to A21 PA5/A21 T [Other than the ab
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Appendix Port Name MCU Operating Mode*1 Reset Hardware Standby Mode Port B 3, 4 T T Program Execution State Sleep Mode Software Standby Mode Bus Release State [OPE = 0, address output] [Address output] [Address output] T A15 to A8 T [Other than the above] [Other than the above] Keep I/O port [OPE = 1, address output] Keep [Other than the above] Keep 3, 7 T T [OPE = 0, address output] [Address output] [Address output] T A15 to A8 T [Other than the above] [Other than the above] Ke
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Appendix Port Name MCU Operating Mode*1 Reset Hardware Standby Mode Port C 3, 7 T T Program Execution State Sleep Mode Software Standby Mode Bus Release State [OPE = 0, address output] [Address output] [Address output] T A7 to A0 T [Other than the above] [Other than the above] Keep I/O port [OPE = 1, address output] Keep [Other than the above] Keep Port D Port E 1, 2, 4 to 6 T T T T D15 toD8 3, 7 T T [Data bus] [Data bus] [Data bus] T T D15 to D8 [Other than the above]
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Appendix Port Name MCU Operating Mode*1 Reset Hardware Standby Mode PF6/AS 1, 2, 4 to 6 H T 3, 7 Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0, AS output] [AS output] [AS output] T AS T [Other than the above] [Other than the above] Keep I/O port T RD, HWR [OPE = 0, RD, HWR output] [RD, HWR output] [RD, HWR output] T T RD, HWR [OPE = 1, RD, HWR output] [Other than the above] [Other than the above] H Keep I/O port [OPE = 0, LWR output]
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Appendix Port Name PF2/LCAS/ DQML*2 MCU Operating Mode*1 Reset Hardware Standby Mode 1 to 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0, LCAS (DQML) output] [LCAS (DQML) output] [LCAS (DQML) output] T LCAS (DQML) T [Other than the above] [Other than the above] Keep I/O port [OPE = 0, UCAS (DQMU) output] [UCAS (DQMU) output] [UCAS (DQMU) output] T UCAS T [Other than the above] [Other than the above] Keep I/O port [WAIT input] [WAIT i
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Appendix Port Name MCU Operating Mode*1 PG5/BACK 1 to 7 Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode T T [BACK output] BACK [BACK output] T BACK [Other than the above] [Other than the above] Keep [BREQO output] [BREQO output] T BREQO BREQO [Other than the above] [Other than the above] [Other than the above] Keep Keep I/O port [CS output] [CS output] PG2/CS2 [OPE = 0, CS output] T CS PG1/CS1 T [Other than the abov
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Appendix Port Name PH3/OE/ CKE/CS7 MCU Operating Mode*1 Reset Hardware Standby Mode 1 to 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0, OE output] [OE output] [OE output] T OE T [CS output] [CS output] [OPE = 1, OE output] T CS H [Other than the above] [Other than the above] [OPE = 0, CS output] Keep I/O port [OPE = 0, CS output] [CS output] [CS output] T CS T [Other than the above] [Other than the above] Keep I/O port T [OPE
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Appendix Port Name MCU Operating Mode*1 Reset Hardware Standby Mode PH0/CS4 1 to 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0, CS output] [CS output] [CS output] T CS T [Other than the above] [Other than the above] Keep I/O port [OPE = 1, CS output] H [Other than the above] Keep Legend: L: Low level H: High level Keep: Input port becomes high-impedance, output port retains state T: High impedance DDR: Data direction register OPE: Output por
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Appendix B.
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Appendix C. Package Dimensions For package dimensions, dimensions described in Renesas Semiconductor Packages have priority. JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KC-A Previous Code FP-144H/FP-144HV MASS[Typ.] 1.4g HD *1 D 108 73 109 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
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Appendix JEITA Package Code P-QFP144-20x20-0.50 RENESAS Code PRQP0144KA-A Previous Code FP-144G/FP-144GV MASS[Typ.] 2.4g HD *1 D 108 73 109 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 72 bp c c1 HE *2 E b1 Terminal cross section Reference Dimension in Millimeters Symbol ZE Min 37 144 36 1 c A2 A ZD F A1 θ L L1 Detail F e *3 y bp x M Figure C.2 Package Dimensions (FP-144G) Rev. 3.
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Index Index 16-Bit Timer Pulse Unit.......................... 521 Buffer Operation ................................. 566 Cascaded Operation ............................ 570 Free-running count operation.............. 560 Input Capture Function ....................... 563 periodic count operation ..................... 560 Phase Counting Mode......................... 577 PWM Modes....................................... 572 Synchronous Operation....................... 564 toggle output ........................
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Index Normal Mode.............................. 412, 421 Register Information ........................... 408 Repeat Mode....................................... 413 Software Activation ............................ 425 vector number for the software activation ........................................................ 406 DMA Controller...................................... 259 Activation by Auto-Request ............... 288 Activation by External Request .......... 287 Block Transfer Mode..................
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Index TCI1U................................................. 584 TCI1V................................................. 584 TCI2U................................................. 584 TCI2V................................................. 584 TCI3V................................................. 584 TCI4U................................................. 584 TCI4V................................................. 584 TCI5U................................................. 584 TCI5V............................
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Index FLMCR2..................... 783, 842, 853, 863 IER................................ 91, 838, 850, 860 INTCR .......................... 88, 838, 850, 860 IOAR .......................... 263, 837, 849, 859 IPR.................88, 834, 835, 845, 856, 857 IrCR ............................ 688, 835, 846, 857 ISCR ............................. 92, 835, 846, 857 ISR ................................ 98, 838, 850, 860 ITSR ............................. 98, 835, 846, 857 MAR ...................
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Index RSTCSR ..................... 653, 842, 853, 863 RTCNT ....................... 152, 837, 848, 859 RTCOR ....................... 152, 837, 848, 859 SAR............................. 405, 834, 844, 856 SBYCR ....................... 822, 838, 850, 860 SCKCR ....................... 812, 838, 850, 860 SCMR ......... 678, 840, 851, 852, 861, 862 SCR............. 670, 840, 851, 852, 861, 862 SEMR ......................... 689, 834, 844, 856 SMR............ 666, 840, 851, 852, 861, 862 SSIER ..................
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Index Rev. 3.
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Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2678 Group, H8S/2678R Group, H8S/2676 F-ZTAT™ Publication Date: 1st Edition, September 2001 Rev.3.00, March 17, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
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H8S/2678 Group, H8S/2678R Group, H8S/2676 F-ZTATTM Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0283-0300