Datasheet

Rev.6.00 Oct.28.2004 page 968 of 1016
REJ09B0138-0600H
Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagram
R
P1nDDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P1nDR
C
QD
P1
n
RDR1
RPOR1
Internal data bus
PPG module
DMA controller
TPU module
Pulse output enable
DMA transfer
acknowledge enable
Pulse output
DMA transfer
acknowledge
Output compare output/
PWM output enable
Output compare output/
PWM output
Input capture input
WDDR1:
WDR1:
RDR1:
RPOR1:
n = 0 or 1
Legend:
Write to P1DDR
Write to P1DR
Read P1DR
Read port 1
Figure C-1 (a) Port 1 Block Diagram (Pins P1
0
and P1
1
)