Datasheet

Rev.6.00 Oct.28.2004 page 761 of 1016
REJ09B0138-0600H
(3) Bus Timing
Table 22-38 lists the bus timing.
Table 22-38 Bus Timing
Condition B: V
CC
= 5.0 V ± 10%, AV
CC
= 5.0 V ± 10%, V
ref
= 4.5 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø= 2 to 20 MHz, T
a
= –20 to +75°C (regular specifications),
T
a
= –40 to +85°C (wide-range specifications)
Condition C: V
CC
= 3.0 to 5.5 V, AV
CC
= 3.0 to 5.5 V, V
ref
= 3.0 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 2 to 13 MHz, T
a
= –20 to +75°C (regular specifications),
T
a
= –40 to +85°C (wide-range specifications)
Condition B Condition C
Item Symbol Min Max Min Max Unit Test Conditions
Address delay time t
AD
— 20 — 40 ns Figure 22-72 to
Address setup time t
AS
0.5 ×
t
cyc
– 15
— 0.5 ×
t
cyc
– 30
—ns
Figure 22-79
Address hold time t
AH
0.5 ×
t
cyc
– 10
— 0.5 ×
t
cyc
– 20
—ns
Precharge time t
PCH
1.5 ×
t
cyc
– 20
— 1.5 ×
t
cyc
– 40
—ns
CS delay time 1 t
CSD1
— 20 — 40 ns
CS delay time 2 t
CSD2
— 20 — 40 ns
CS delay time 3 t
CSD3
— 25 — 40 ns
AS delay time t
ASD
— 20 — 40 ns
RD delay time 1 t
RSD1
— 20 — 40 ns
RD delay time 2 t
RSD2
— 20 — 40 ns
CAS delay time t
CASD
— 20 — 40 ns
Read data setup time t
RDS
15 — 30 — ns
Read data hold time t
RDH
0—0—ns
Read data access
time 1
t
ACC1
— 1.0 ×
t
cyc
– 25
— 1.0 ×
t
cyc
– 50
ns
Read data access
time 2
t
ACC2
— 1.5 ×
t
cyc
– 25
— 1.5 ×
t
cyc
– 50
ns
Read data access
time 3
t
ACC3
— 2.0 ×
t
cyc
– 25
— 2.0 ×
t
cyc
– 50
ns
Read data access
time 4
t
ACC4
— 2.5 ×
t
cyc
– 25
— 2.5 ×
t
cyc
– 50
ns
Read data access
time 5
t
ACC5
— 3.0 ×
t
cyc
– 25
— 3.0 ×
t
cyc
– 50
ns
WR delay time 1 t
WRD1
— 20 — 40 ns
WR delay time 2 t
WRD2
— 20 — 40 ns
WR pulse width 1 t
WSW1
1.0 ×
t
cyc
– 20
— 1.0 ×
t
cyc
– 40
—ns
WR pulse width 2 t
WSW2
1.5 ×
t
cyc
– 20
— 1.5 ×
t
cyc
– 40
—ns