Datasheet

Rev.6.00 Oct.28.2004 page 22 of 1016
REJ09B0138-0600H
• Power-down state
 Transition to power-down state by SLEEP instruction
 CPU clock speed selection
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU.
• Number of execution states
The number of exection states of the MULXU and MULXS instructions.
Internal Operation
Instruction Mnemonic H8S/2600 H8S/2000
MULXU MULXU.B Rs, Rd 3 12
MULXU.W Rs, ERd 4 20
MULXS MULXS.B Rs, Rd 4 13
MULXS.W Rs, ERd 5 21
There are also differences in the address space, CCR and EXR functions, power-down state, etc., depending on the
product.
2.1.3 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
 Eight 16-bit expanded registers, and one 8-bit control register, have been added.
• Expanded address space
 Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
 The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 Signed multiply and divide instructions have been added.
 2-bit shift instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.
• Higher speed
 Basic instructions execute twice as fast.