Datasheet

Rev.6.00 Oct.28.2004 page xi of xxiv
REJ09B0138-0600H
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK).....................................................................................84
5.2.3 IRQ Enable Register (IER) ........................................................................................................................... 85
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..............................................................................86
5.2.5 IRQ Status Register (ISR).............................................................................................................................86
5.3 Interrupt Sources.........................................................................................................................................................87
5.3.1 External Interrupts......................................................................................................................................... 87
5.3.2 Internal Interrupts ..........................................................................................................................................88
5.3.3 Interrupt Exception Handling Vector Table..................................................................................................88
5.4 Interrupt Operation..................................................................................................................................................... 91
5.4.1 Interrupt Control Modes and Interrupt Operation ......................................................................................... 91
5.4.2 Interrupt Control Mode 0...............................................................................................................................93
5.4.3 Interrupt Control Mode 2...............................................................................................................................95
5.4.4 Interrupt Exception Handling Sequence ....................................................................................................... 97
5.4.5 Interrupt Response Times..............................................................................................................................98
5.5 Usage Notes................................................................................................................................................................99
5.5.1 Contention between Interrupt Generation and Disabling..............................................................................99
5.5.2 Instructions that Disable Interrupts ............................................................................................................... 99
5.5.3 Times when Interrupts are Disabled............................................................................................................100
5.5.4 Interrupts during Execution of EEPMOV Instruction................................................................................. 100
5.6 DTC and DMAC Activation by Interrupt.................................................................................................................100
5.6.1 Overview .....................................................................................................................................................100
5.6.2 Block Diagram............................................................................................................................................. 101
5.6.3 Operation..................................................................................................................................................... 101
5.6.4 Note on Use.................................................................................................................................................102
Section 6 Bus Controller...................................................................................................................103
6.1 Overview................................................................................................................................................................... 103
6.1.1 Features ....................................................................................................................................................... 103
6.1.2 Block Diagram............................................................................................................................................. 105
6.1.3 Pin Configuration ........................................................................................................................................106
6.1.4 Register Configuration ................................................................................................................................107
6.2 Register Descriptions................................................................................................................................................108
6.2.1 Bus Width Control Register (ABWCR)......................................................................................................108
6.2.2 Access State Control Register (ASTCR)..................................................................................................... 109
6.2.3 Wait Control Registers H and L (WCRH, WCRL).....................................................................................110
6.2.4 Bus Control Register H (BCRH).................................................................................................................113
6.2.5 Bus Control Register L (BCRL)..................................................................................................................114
6.2.6 Memory Control Register (MCR)............................................................................................................... 116
6.2.7 DRAM Control Register (DRAMCR).........................................................................................................118
6.2.8 Refresh Timer/Counter (RTCNT)...............................................................................................................119
6.2.9 Refresh Time Constant Register (RTCOR)................................................................................................. 120
6.3 Overview of Bus Control..........................................................................................................................................121
6.3.1 Area Partitioning ......................................................................................................................................... 121
6.3.2 Bus Specifications.......................................................................................................................................122
6.3.3 Memory Interfaces....................................................................................................................................... 123
6.3.4 Advanced Mode........................................................................................................................................... 123
6.3.5 Chip Select Signals..........................................................................................................................................124
6.4 Basic Bus Interface................................................................................................................................................... 125
6.4.1 Overview .....................................................................................................................................................125
6.4.2 Data Size and Data Alignment ....................................................................................................................125
6.4.3 Valid Strobes ..............................................................................................................................................127
6.4.4 Basic Timing ............................................................................................................................................... 128