Datasheet

Section 22 Electrical Characteristics
Rev.6.00 Sep. 27, 2007 Page 960 of 1268
REJ09B0220-0600
Condition A Condition B
Test
Item Symbol Min Max Min Max Unit Conditions
SCI Asynchronous t
Scyc
4 — 4 — t
cyc
Figure 22.28
Input clock
cycle
Synchronous 6 — 6 —
Input clock pulse width t
SCKW
0.4 0.6 0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 — 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5 — 1.5
Transmit data delay time t
TXD
— 50 — 40 ns Figure 22.29
Receive data setup time
(synchronous)
t
RXS
50 — 40 — ns
Receive data hold time
(synchronous)
t
RXH
50 — 40 — ns
A/D
converter
Trigger input setup time t
TRGS
30 — 30 — ns Figure 22.30
φ
Ports 1 to 6,
A
to G
(read)
t
PRS
T
1
T
2
t
PWD
t
PRH
Ports 1, 2, 3,
5, 6, A to G
(write)
Figure 22.20 I/O Port Input/Output Timing
φ
PO
15
to PO
0
t
POD
Figure 22.21 PPG Output Timing