Datasheet

Section 22 Electrical Characteristics
Rev.6.00 Sep. 27, 2007 Page 946 of 1268
REJ09B0220-0600
Condition A Condition B
Item Symbol Min Max Min Max Unit Test Conditions
WR delay time 1 t
WRD1
— 20 — 15 ns
WR delay time 2 t
WRD2
— 20 — 15 ns
Figures 22.6 to
22.13
WR pulse width 1 t
WSW1
1.0 ×
t
cyc
– 20
— 1.0 ×
t
cyc
– 15
— ns
WR pulse width 2 t
WSW2
1.5 ×
t
cyc
– 20
— 1.5 ×
t
cyc
– 15
— ns
Write data delay time t
WDD
— 30 — 20 ns
Write data setup time t
WDS
0.5 ×
t
cyc
– 20
— 0.5 ×
t
cyc
– 15
— ns
Write data hold time t
WDH
0.5 ×
t
cyc
– 10
— 0.5 ×
t
cyc
– 8
— ns
WR setup time
*
t
WCS
0.5 ×
t
cyc
– 10
— 0.5 ×
t
cyc
– 10
— ns
WR hold time
*
t
WCH
0.5 ×
t
cyc
– 10
— 0.5 ×
t
cyc
– 10
— ns
CAS setup time
*
t
CSR
0.5 ×
t
cyc
– 10
— 0.5 ×
t
cyc
– 8
— ns Figure 22.10
WAIT setup time t
WTS
30 — 25 — ns Figure 22.8
WAIT hold time t
WTH
5 — 5 — ns
BREQ setup time t
BRQS
30 — 30 — ns Figure 22.14
BACK delay time t
BACD
— 15 — 15 ns
Bus floating time t
BZD
— 50 — 40 ns
BREQO delay time t
BRQOD
— 30 — 25 ns Figure 22.15
Note: * The DRAM interface is not supported in the H8S/2321.