Datasheet

Section 20 Clock Pulse Generator
Rev.6.00 Sep. 27, 2007 Page 917 of 1268
REJ09B0220-0600
Table 20.4 External Clock Input Conditions
V
CC
= 2.7 V
to 3.6 V
V
CC
= 3.0 V
to 3.6 V
Item Symbol Min Max Min Max Unit
Test
Conditions
External clock input
low pulse width
t
EXL
20 — 10 — ns Figure 20.6
External clock input
high pulse width
t
EXH
20 — 10 — ns
External clock rise time t
EXr
— 5 — 5 ns
External clock fall time t
EXf
— 5 — 5 ns
t
CL
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHz Figure 22-2 Clock low pulse width
level
80 — 80 — ns φ < 5 MHz
Clock high pulse width t
CH
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHz
level 80 — 80 — ns φ < 5 MHz
EXTAL
XTAL
External clock input
Open
(a) XTAL pin left open
EXTAL
XTAL
External clock input
(b) Complementary clock input at XTAL pin
Figure 20.6 External Clock Input Timing