Datasheet

Section 20 Clock Pulse Generator
Rev.6.00 Sep. 27, 2007 Page 914 of 1268
REJ09B0220-0600
Description
Bit 2
SCK2
Bit 1
SCK1
Bit 0
SCK0
DIV = 0 DIV = 1
0 0 0 Bus master is in high-speed
mode (Initial value)
Bus master is in high-speed
mode (Initial value)
1 Medium-speed clock is φ/2 Clock supplied to entire chip is φ/2
1 0 Medium-speed clock is φ/4 Clock supplied to entire chip is φ/4
1 Medium-speed clock is φ/8 Clock supplied to entire chip is φ/8
1 0 0 Medium-speed clock is φ/16 —
1 Medium-speed clock is φ/32 —
1 — — —
20.3 Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
20.3.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure
20.2. Select the damping resistance R
d
according to table 20.2. An AT-cut parallel-resonance
crystal should be used.
EXTAL
XTAL
R
d
C
L2
C
L1
C
L1
= C
L2
= 10 to 22 pF
Figure 20.2 Connection of Crystal Resonator (Example)
Table 20.2 Damping Resistance Value
Frequency (MHz) 2 4 8 12 16 20 25
R
d
(Ω) 6.8 k 500 200 0 0 0 0