Datasheet

Section 20 Clock Pulse Generator
Rev.6.00 Sep. 27, 2007 Page 912 of 1268
REJ09B0220-0600
20.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR. Table 20.1 shows the register configuration.
Table 20.1 Clock Pulse Generator Register
Name Abbreviation R/W Initial Value Address
*
System clock control register SCKCR R/W H'00 H'FF3A
Note: * Lower 16 bits of the address.
20.2 Register Descriptions
20.2.1 System Clock Control Register (SCKCR)
Bit : 7 6 5 4 3 2 1 0
PSTOP — DIV — — SCK2 SCK1 SCK0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W — — R/W R/W R/W
SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode
in which the bus master runs on a medium-speed clock and the other supporting modules run on
the high-speed clock, and a function that allows the medium-speed mode to be disabled and the
clock division ratio to be changed for the entire chip.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Description
Bit 7
PSTOP Normal Operation Sleep Mode
Software
Standby Mode
Hardware
Standby Mode
0 φ output (Initial value) φ output Fixed high High impedance
1 Fixed high Fixed high Fixed high High impedance
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.