Datasheet

Section 16 A/D Converter (8 Analog Input Channel Version)
Rev.6.00 Sep. 27, 2007 Page 706 of 1268
REJ09B0220-0600
16.2.2 A/D Control/Status Register (ADCSR)
Bit : 7 6 5 4 3 2 1 0
ADF ADIE ADST SCAN CKS CH2 CH1 CH0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/(W)
*
R/W R/W R/W R/W R/W R/W R/W
Note: * Only 0 can be written to bit 7, to clear this flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows
the status of the operation.
ADCSR is initialized to H'00 by a reset, and in standby mode or module stop mode.
Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7
ADF Description
0 [Clearing conditions] (Initial value)
• When 0 is written to the ADF flag after reading ADF = 1
• When the DMAC
*
or DTC is activated by an ADI interrupt and ADDR is read
1 [Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
Note: * The DMAC is not supported in the H8S/2321.
Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests
at the end of A/D conversion.
Bit 6
ADIE Description
0 A/D conversion end interrupt (ADI) request disabled (Initial value)
1 A/D conversion end interrupt (ADI) request enabled