Datasheet

Section 15 Smart Card Interface
Rev.6.00 Sep. 27, 2007 Page 699 of 1268
REJ09B0220-0600
• Retransfer operation when SCI is in transmit mode
Figure 15.12 illustrates the retransfer operation when the SCI is in transmit mode.
[6] If an error signal is sent back from the receiving end after transmission of one frame is
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next
parity bit is sampled.
[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality
is received.
[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
[9] If an error signal is not sent back from the receiving end, transmission of one frame, including
a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE
bit in SCR is enabled at this time, a TXI interrupt request is generated.
If data transfer by the DMAC
*
or DTC by means of the TXI source is enabled, the next data
can be written to TDR automatically. When data is written to TDR by the DMAC
*
or DTC,
the TDRE bit is automatically cleared to 0.
Note: * The DMAC is not supported in the H8S/2321.
D0D1D2D3D4D5D6D7Dp DE DsD0D1D2D3D4D5D6D7Dp
(DE)
DsD0D1D2D3D4Ds
Transfer
frame n+1
Retransferred framenth transfer frame
TDRE
TEND
[6]
FER/ERS
Transfer to TSR from TDR
[7] [9]
[8]
Transfer to TSR from TDR
Transfer to TSR
from TDR
Figure 15.12 Retransfer Operation in SCI Transmit Mode