Datasheet

Section 15 Smart Card Interface
Rev.6.00 Sep. 27, 2007 Page 689 of 1268
REJ09B0220-0600
(1) Data write
TDR
TSR
(shift register)
Data 1
(2) Transfer from
TDR to TSR
Data 1 Data 1 ; Data remains in TDR
(3) Serial data output
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has
been completed.
In case of normal transmission: TEND flag is set
In case of transmit error: ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
I/O signal line output
Data 1
Data 1
Figure 15.5 Relation Between Transmit Operation and Internal Registers
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp I/O data
12.5 etu
TXI
(TEND interrupt)
11.0 etu
DE
Guard
time
When GM = 1
Legend:
Ds: Start bit
D0 to D7: Data bits
Dp: Parity bit
DE: Error signal
Note: etu: Elementary time unit (time for transfer of 1 bit)
When GM = 0
Figure 15.6 TEND Flag Generation Timing in Transmission