Datasheet

Section 15 Smart Card Interface

Rev.6.00 Sep. 27, 2007 Page 674 of 1268

REJ09B0220-0600

Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial

Status Register (SSR).

However, the setting conditions for the TEND bit, are as shown below.

Bit 2

TEND

Description

Indicates transfer in progress

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DMAC

or DTC is activated by a TXI interrupt and writes data to TDR

1 Indicates transfer complete (Initial value)

[Setting conditions]

• Upon reset, and in standby mode or module stop mode

• When the TE bit in SCR is 0 and the ERS bit is also 0

• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a

1-byte serial character when GM = 0 and BLK = 0

• When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a

1-byte serial character when GM = 0 and BLK = 1

• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a

1-byte serial character when GM = 1 and BLK = 0

• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a

1-byte serial character when GM = 1 and BLK = 1

Notes: etu: Elementary time unit (time for transfer of 1 bit)

* The DMAC is not supported in the H8S/2321.