Datasheet

Section 15 Smart Card Interface
Rev.6.00 Sep. 27, 2007 Page 673 of 1268
REJ09B0220-0600
15.2.2 Serial Status Register (SSR)
Bit : 7 6 5 4 3 2 1 0
TDRE RDRF ORER ERS PER TEND MPB MPBT
Initial value : 1 0 0 0 0 1 0 0
R/W : R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R R R/W
Note: * Only 0 can be written to bits 7 to 3, to clear these flags.
Bit 4 of SSR has a different function in smart card interface mode. Coupled with this, the setting
conditions for bit 2, TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial
Status Register (SSR).
Bit 4—Error Signal Status (ERS): In smart card interface mode, bit 4 indicates the status of the
error signal sent back from the receiving end in transmission. Framing errors are not detected in
smart card interface mode.
Bit 4
ERS Description
0 Indicates data received normally with no error signal (Initial value)
[Clearing conditions]
• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
1 Indicates an error signal was sent showing detection of a parity error at the receiving
side
[Setting condition]
When the low level of the error signal is sampled
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous
state.