Datasheet

Section 14 Serial Communication Interface (SCI)
Rev.6.00 Sep. 27, 2007 Page 661 of 1268
REJ09B0220-0600
Restrictions on Use of DMAC
*
or DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 φ clock cycles after TDR is updated by the DMAC
*
or DTC.
Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated.
(Figure 14.22)
• When RDR is read by the DMAC
*
or DTC, be sure to set the activation source to the relevant
SCI receive-data-full interrupt (RXI).
Note: * The DMAC is not supported in the H8S/2321.
t
D0
LSB
Serial data
SCK
D1
D3 D4 D5D2 D6 D7
Note: When operating on an external clock, set t > 4 clocks.
TDRE
Figure 14.22 Example of Synchronous Transmission Using DTC