Datasheet

Section 2 CPU
Rev.6.00 Sep. 27, 2007 Page 34 of 1268
REJ09B0220-0600
• High-speed operation
⎯ All frequently-used instructions execute in one or two states
⎯ Maximum clock rate: 25 MHz
⎯ 8/16/32-bit register-register add/subtract: 40 ns
⎯ 8 × 8-bit register-register multiply: 480 ns
⎯ 16 ÷ 8-bit register-register divide: 480 ns
⎯ 16 × 16-bit register-register multiply: 800 ns
⎯ 32 ÷ 16-bit register-register divide: 800 ns
• CPU operating mode
⎯ Advanced mode
• Power-down state
⎯ Transition to power-down state by SLEEP instruction
⎯ CPU clock speed selection
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of exection states of the MULXU and MULXS instructions.
Internal Operation
Instruction Mnemonic H8S/2600 H8S/2000
MULXU MULXU.B Rs, Rd 3 12
MULXU.W Rs, ERd 4 20
MULXS MULXS.B Rs, Rd 4 13
MULXS.W Rs, ERd 5 21
There are also differences in the address space, CCR and EXR functions, power-down state, etc.,
depending on the product.