Datasheet

Section 14 Serial Communication Interface (SCI)
Rev.6.00 Sep. 27, 2007 Page 598 of 1268
REJ09B0220-0600
• Full-duplex communication capability
⎯ The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
⎯ Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
• Choice of LSB-first or MSB-first transfer
⎯ Can be selected regardless of the communication mode
*
1
(except in the case of
asynchronous mode 7-bit data)
• Built-in baud rate generator allows any bit rate to be selected
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
• Four interrupt sources
⎯ Four interrupt sources—transmit-data-empty, transmit-end, receive-data-full, and receive
error—that can issue requests independently
⎯ The transmit-data-empty and receive-data-full interrupts can activate the DMA controller
(DMAC)
*
2
or data transfer controller (DTC) to execute data transfer
• Module stop mode can be set
⎯ As the initial setting, SCI operation is halted. Register access is enabled by exiting module
stop mode
Notes: 1. Descriptions in this section refer to LSB-first transfer.
2. The DMAC is not supported in the H8S/2321.