Datasheet

Section 13 Watchdog Timer
Rev.6.00 Sep. 27, 2007 Page 587 of 1268
REJ09B0220-0600
13.2.3 Reset Control/Status Register (RSTCSR)
Bit : 7 6 5 4 3 2 1 0
WOVF RSTE — — — — — —
Initial value : 0 0 0 1 1 1 1 1
R/W : R/(W)
*
R/W R/W — — — — —
Note: * Only 0 can be written, to clear the flag.
RSTCSR is an 8-bit readable/writable
*
register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
see section 13.2.4, Notes on Register Access.
Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed
(changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer
mode.
Bit 7
WOVF Description
0 [Clearing condition] (Initial value)
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
1 [Setting condition]
Set when TCNT overflows (changes from H'FF to H'00) during watchdog timer
operation
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the chip if
TCNT overflows during watchdog timer operation.
Bit 6
RSTE Description
0 Reset signal is not generated if TCNT overflows
*
(Initial value)
1 Reset signal is generated if TCNT overflows
Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset.