Datasheet

Section 13 Watchdog Timer
Rev.6.00 Sep. 27, 2007 Page 583 of 1268
REJ09B0220-0600
13.1.3 Pin Configuration
Table 13.1 describes the WDT output pin.
Table 13.1 WDT Pin
Name Symbol I/O Function
Watchdog timer overflow WDTOVF
*
Output Outputs counter overflow signal in watchdog
timer mode
Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions.
13.1.4 Register Configuration
The WDT has three registers, as summarized in table 13.2. These registers control clock selection,
WDT mode switching, and the reset signal.
Table 13.2 WDT Registers
Address
*
1
Name Abbreviation R/W Initial Value Write
*
2
Read
Timer control/status register TCSR R/(W)
*
3
H'18 H'FFBC H'FFBC
Timer counter TCNT R/W H'00 H'FFBC H'FFBD
Reset control/status register RSTCSR R/(W)
*
3
H'1F H'FFBE H'FFBF
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 13.2.4, Notes on Register Access.
3. Only a write of 0 is permitted to bit 7, to clear the flag.