Datasheet

Section 12 8-Bit Timers
Rev.6.00 Sep. 27, 2007 Page 576 of 1268
REJ09B0220-0600
12.6.3 Contention between TCOR Write and Compare Match
During the T
2
state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs.
Figure 12.12 shows this operation.
φ
A
ddress TCOR address
Internal write signal
TCNT
TCOR
NM
T
1
T
2
TCOR write cycle by CPU
TCOR write data
N N+1
Compare match signal
Prohibited
Figure 12.12 Contention between TCOR Write and Compare Match