Datasheet

Section 12 8-Bit Timers
Rev.6.00 Sep. 27, 2007 Page 574 of 1268
REJ09B0220-0600
12.6 Usage Notes
Note that the following kinds of contention can occur in the 8-bit timer module.
12.6.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 12.10 shows this operation.
φ
A
ddress TCNT address
Internal write signal
Counter clear signal
TCNT
N H'00
T
1
T
2
TCNT write cycle by CPU
Figure 12.10 Contention between TCNT Write and Clear