Datasheet

Section 11 Programmable Pulse Generator (PPG)
Rev.6.00 Sep. 27, 2007 Page 539 of 1268
REJ09B0220-0600
Address H'FF4D
Bit : 7 6 5 4 3 2 1 0
NDR7 NDR6 NDR5 NDR4 — — — —
Initial value : 0 0 0 0 1 1 1 1
R/W : R/W R/W R/W R/W — — — —
Address H'FF4F
Bit : 7 6 5 4 3 2 1 0
— — — — NDR3 NDR2 NDR1 NDR0
Initial value : 1 1 1 1 0 0 0 0
R/W : — — — — R/W R/W R/W R/W
11.2.5 PPG Output Control Register (PCR)
Bit : 7 6 5 4 3 2 1 0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value : 1 1 1 1 1 1 1 1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a
group-by-group basis.
PCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match that triggers pulse output group 3 (pins PO15 to PO12).
Description
Bit 7
G3CMS1
Bit 6
G3CMS0 Output Trigger for Pulse Output Group 3
0 0 Compare match in TPU channel 0
1 Compare match in TPU channel 1
1 0 Compare match in TPU channel 2
1 Compare match in TPU channel 3 (Initial value)