Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 128 (14x20) 16-Bit 25 MHz I/O number 86

Section 11 Programmable Pulse Generator (PPG)

Rev.6.00 Sep. 27, 2007 Page 532 of 1268

REJ09B0220-0600

11.1.2 Block Diagram

Figure 11.1 shows a block diagram of the PPG.

Compare match signals

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

PO7

PO6

PO5

PO4

PO3

PO2

PO1

PO0

Legend:

PMR:

PCR:

NDERH:

NDERL:

NDRH:

NDRL:

PODRH:

PODRL:

PPG output mode register

PPG output control register

Next data enable register H

Next data enable register L

Next data register H

Next data register L

Output data register H

Output data register L

Internal

data bus

Pulse output

pins, group 3

Pulse output

pins, group 2

Pulse output

pins, group 1

Pulse output

pins, group 0

PODRH

PODRL

NDRH

NDRL

Control logic

NDERH

PMR

NDERL

PCR

Figure 11.1 Block Diagram of PPG