Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 528 of 1268
REJ09B0220-0600
Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T
2
state of a buffer write cycle, the buffer operation takes precedence and the
write to the buffer register is not performed.
Figure 10.55 shows the timing in this case.
Input capture
signal
Write signal
A
ddress
φ
TCNT
Buffer register write cycle
T
1
T
2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 10.55 Contention between Buffer Register Write and Input Capture