Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 526 of 1268
REJ09B0220-0600
Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T
1
state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 10.53 shows the timing in this case.
Input capture
signal
Read signal
A
ddress
φ
TGR address
TGR
TGR read cycle
T
1
T
2
M
Internal
data bus
X M
Figure 10.53 Contention between TGR Read and Input Capture