Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 525 of 1268
REJ09B0220-0600
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T
2
state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
data prior to the write.
Figure 10.52 shows the timing in this case.
Compare
match signal
Write signal
A
ddress
φ
Buffer register
address
Buffer
register
TGR write cycle
T
1
T
2
N
TGR
N M
Buffer register write data
Figure 10.52 Contention between Buffer Register Write and Compare Match