Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 524 of 1268
REJ09B0220-0600
Contention between TGR Write and Compare Match: If a compare match occurs in the T
2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 10.51 shows the timing in this case.
Compare
match signal
Write signal
A
ddress
φ
TGR address
TCNT
TGR write cycle
T
1
T
2
N M
TGR write data
TGR
N N+1
Inhibited
Figure 10.51 Contention between TGR Write and Compare Match