Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 523 of 1268
REJ09B0220-0600
Contention between TCNT Write and Increment Operations: If incrementing occurs in the T
2
state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 10.50 shows the timing in this case.
TCNT input
clock
Write signal
A
ddress
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N M
TCNT write data
Figure 10.50 Contention between TCNT Write and Increment Operations