Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 522 of 1268
REJ09B0220-0600
Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T
2
state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 10.49 shows the timing in this case.
Counter clear
signal
Write signal
A
ddress
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N H'0000
Figure 10.49 Contention between TCNT Write and Clear Operations