Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 520 of 1268
REJ09B0220-0600
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC
*
is activated, the flag is cleared automatically. Figure 10.46
shows the timing for status flag clearing by the CPU, and figure 10.47 shows the timing for status
flag clearing by the DTC or DMAC
*
.
Note: * The DMAC is not supported in the H8S/2321.
Status flag
Write signal
A
ddress
φ
TSR address
Interrupt
request
signal
TSR write cycle
T
1
T
2
Figure 10.46 Timing for Status Flag Clearing by CPU
Interrupt
request
signal
Note: * The DMAC is not supported in the H8S/2321.
Status flag
A
ddress
φ
Source address
DTC/DMAC
*
read cycle
T
1
T
2
Destination
address
T
1
T
2
DTC/DMAC
*
write cycle
Figure 10.47 Timing for Status Flag Clearing by DTC/DMAC Activation